Analog Integrated Circuits and Signal Processing

, Volume 49, Issue 2, pp 131–140

A bang-bang PLL employing dynamic gain control for low jitter and fast lock times

  • Michael J. Chan
  • Adam Postula
  • Yong Ding
  • Lech Jozwiak
Article

DOI: 10.1007/s10470-006-7581-3

Cite this article as:
Chan, M.J., Postula, A., Ding, Y. et al. Analog Integr Circ Sig Process (2006) 49: 131. doi:10.1007/s10470-006-7581-3

Abstract

Bang-bang phase detector based PLLs are simple to design, suffer no systematic phase error, and can run at the highest speed a process can make a working flip-flop. For these reasons designers are employing them in the design of very high speed Clock Data Recovery (CDR) architectures. The major drawback of this class of PLL is the inherent jitter due to quantized phase and frequency corrections. Reducing loop gain can proportionally improve jitter performance, but also reduces locking time and pull-in range. This paper presents a novel PLL design that dynamically scales its gain in order to achieve fast lock times while improving jitter performance in lock. Under certain circumstances the design also demonstrates improved capture range. This paper also analyses the behaviour of a bang-bang type PLL when far from lock, and demonstrates that the pull-in range is proportional to the square root of the PLL loop gain.

Keywords

Bang-bang PLL Binary PLL Gain control Capture range Jitter 

Copyright information

© Springer Science + Business Media, LLC 2006

Authors and Affiliations

  • Michael J. Chan
    • 1
  • Adam Postula
    • 1
  • Yong Ding
    • 2
  • Lech Jozwiak
    • 3
  1. 1.University of QueenslandAustralia
  2. 2.Nanosilicon Pty Ltd.Australia
  3. 3.Eindhoven UniversityThe Netherlands

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