A bang-bang PLL employing dynamic gain control for low jitter and fast lock times
Purchase on Springer.com
$39.95 / €34.95 / £29.95*
Rent the article at a discountRent now
* Final gross prices may vary according to local VAT.
Bang-bang phase detector based PLLs are simple to design, suffer no systematic phase error, and can run at the highest speed a process can make a working flip-flop. For these reasons designers are employing them in the design of very high speed Clock Data Recovery (CDR) architectures. The major drawback of this class of PLL is the inherent jitter due to quantized phase and frequency corrections. Reducing loop gain can proportionally improve jitter performance, but also reduces locking time and pull-in range. This paper presents a novel PLL design that dynamically scales its gain in order to achieve fast lock times while improving jitter performance in lock. Under certain circumstances the design also demonstrates improved capture range. This paper also analyses the behaviour of a bang-bang type PLL when far from lock, and demonstrates that the pull-in range is proportional to the square root of the PLL loop gain.
- M. Ramezani and C.A.T. Salama, “A 10 Gb/s CDR with a half-rate bang-bang phase detector,” presented at Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS ‘03., 2003.
- H. Nosaka, K. Ishii, T. Enoki, and T. Shibata, “A 10-Gb/s data-pattern independent clock and data recovery circuit with a two-mode phase comparator,” Solid-State Circuits, IEEE Journal, vol. 38, pp. 192–197, 2003. CrossRef
- J. Lee, K.S. Kundert, and B. Razavi, “Analysis and modelling of bang-bang clock and data recovery circuits.” Solid-State Circuits, IEEE Journal, vol. 39, pp. 1571–1580, 2004. CrossRef
- D. Messerschmitt, “Frequency detectors for PLL acquisition in timing and carrier recovery.” Communications, IEEE Transactions on legacy, pre - 1988], vol. 27, pp. 1288–1295, 1979.
- M. Ramezani and C.A.T. Salama, “An improved bang-bang phase detector for clock and data recovery applications.” Presented at Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on, 2001.
- R.C. Walker, “Designing bang-bang PLLs for clock and data recovery in serial data transmission systems.” In Phase-Locking in High Performance Systems---From Devices to Architectures, B. Razavi, (Eds.), IEEE Press, 2003, pp. 34–45.
- N. DaDalt, “A design-oriented study of the nonlinear dynamics of digital bang-bang PLLs.” Circuits and Systems I: Regular Papers, IEEE Transactions on [see also Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on], vol. 52, pp. 21–31, 2005. CrossRef
- M. Ramezani and C.A.T. Salama, “Analysis of a half-rate bang-bang phase-locked-loop.” Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on [see also Circuits and Systems II: Express Briefs, IEEE Transactions on], vol. 49, pp. 505–509, 2002. CrossRef
- M. Ramezani and C.A.T. Salama, “Jitter analysis of a PLL-based CDR with a bang-bang phase detector.” Presented at Circuits and Systems, 2002. MWSCAS-2002. The 2002 45th Midwest Symposium on, 2002.
- A bang-bang PLL employing dynamic gain control for low jitter and fast lock times
Analog Integrated Circuits and Signal Processing
Volume 49, Issue 2 , pp 131-140
- Cover Date
- Print ISSN
- Online ISSN
- Kluwer Academic Publishers
- Additional Links
- Bang-bang PLL
- Binary PLL
- Gain control
- Capture range
- Industry Sectors