Mathematical Programming

, Volume 121, Issue 2, pp 201–220

Optimal wire ordering and spacing in low power semiconductor design

FULL LENGTH PAPER Series A

DOI: 10.1007/s10107-008-0231-z

Cite this article as:
Gritzmann, P., Ritter, M. & Zuber, P. Math. Program. (2010) 121: 201. doi:10.1007/s10107-008-0231-z

Abstract

A key issue for high integration circuit design in the semiconductor industry are power constraints that stem from the need for heat removal and reliability or battery lifetime limitations. As the power consumption depends heavily on the capacitances between adjacent wires, determining the optimal ordering and spacing of parallel wires is an important issue in the design of low power chips. As it turns out, optimal wire spacing is a convex optimization problem, whereas the optimal wire ordering is combinatorial in nature, containing (a special class of) the Minimum Hamilton Path problem. While the latter is \({\mathcal{NP}}\)-hard in general, the present paper provides an \({\mathcal{O}{(N \log N)}}\) algorithm that solves the coupled ordering and spacing problem for N parallel wires to optimality.

Keywords

Optimal wire placement Convex programming Combinatorial optimization Hamilton path 

Mathematics Subject Classification (2000)

90C27 90C25 90C90 

Copyright information

© Springer-Verlag 2008

Authors and Affiliations

  1. 1.Department of MathematicsTechnische Universität MünchenMünchenGermany
  2. 2.Department of Electrical Engineering and Information TechnologyTechnische Universität MünchenMünchenGermany
  3. 3.Interuniversity Microelectronics Centre (IMEC), Nomadic Embedded SystemsLeuvenBelgium