International Journal on Software Tools for Technology Transfer

, Volume 4, Issue 2, pp 211–223

A systematic incrementalization technique and its application to hardware design

  • Steven D. Johnson
  • Yanhong A. Liu
  • Yuchen Zhang
Regular contribution

DOI: 10.1007/s100090100067

Cite this article as:
Johnson, S., Liu, Y. & Zhang, Y. STTT (2003) 4: 211. doi:10.1007/s100090100067


A systematic transformation method based on incrementalization and value caching generalizes a broad family of program optimizations. It yields significant performance improvements in many program classes, including iterative schemes that characterize hardware specifications. CACHET is an interactive incrementalization tool. Although incrementalization is highly structured and automatable, better results are obtained through interaction, where the main task is to guide term rewriting based on data-specific identities. Incrementalization specialized to iteration corresponds to strength reduction, a familiar program improvement technique. This correspondence is illustrated by the derivation of a hardware-efficient nonrestoring square-root algorithm, which has also served as an example of theorem prover-based implementation verification.

Key words: Formal methods – Hardware verification – Design derivation – Formal synthesis – Transformational programming – Floating point operations

Copyright information

© Springer-Verlag 2003

Authors and Affiliations

  • Steven D. Johnson
    • 1
  • Yanhong A. Liu
    • 2
  • Yuchen Zhang
    • 3
  1. 1.Indiana University Computer Science Department, Indiana University, Indiana, USA; E-mail: sjohnson@cs.indiana.eduUS
  2. 2.Computer Science Department, State University of New York at Stony Brook, New York, USA; E-mail: liu@cs.sunysb.eduUS
  3. 3.Motorola Corp., Schaumburg, Illinois, USAUS