The VLDB Journal

, Volume 25, Issue 5, pp 625–650

Characterization of the Impact of Hardware Islands on OLTP

  • Danica Porobic
  • Ippokratis Pandis
  • Miguel Branco
  • Pınar Tözün
  • Anastasia Ailamaki
Special Issue Paper

DOI: 10.1007/s00778-015-0413-2

Cite this article as:
Porobic, D., Pandis, I., Branco, M. et al. The VLDB Journal (2016) 25: 625. doi:10.1007/s00778-015-0413-2

Abstract

Modern hardware is abundantly parallel and increasingly heterogeneous. The numerous processing cores have non-uniform access latencies to the main memory and processor caches, which causes variability in the communication costs. Unfortunately, database systems mostly assume that all processing cores are the same and that microarchitecture differences are not significant enough to appear in critical database execution paths. As we demonstrate in this paper, however, non-uniform core topology does appear in the critical path and conventional database architectures achieve suboptimal and even worse, unpredictable performance. We perform a detailed performance analysis of OLTP deployments in servers with multiple cores per CPU (multicore) and multiple CPUs per server (multisocket). We compare different database deployment strategies where we vary the number and size of independent database instances running on a single server, from a single shared-everything instance to fine-grained shared-nothing configurations. We quantify the impact of non-uniform hardware on various deployments by (a) examining how efficiently each deployment uses the available hardware resources and (b) measuring the impact of distributed transactions and skewed requests on different workloads. We show that no strategy is optimal for all cases and that the best choice depends on the combination of hardware topology and workload characteristics. Finally, we argue that transaction processing systems must be aware of the hardware topology in order to achieve predictably high performance.

Keywords

Islands Shared-everything Shared-nothing OLTP Multisocket multicores Non-uniform hardware topology 

Copyright information

© Springer-Verlag Berlin Heidelberg 2015

Authors and Affiliations

  • Danica Porobic
    • 1
  • Ippokratis Pandis
    • 2
  • Miguel Branco
    • 3
  • Pınar Tözün
    • 4
  • Anastasia Ailamaki
    • 1
    • 3
  1. 1.School of Computer and Communication SciencesÉcole Polytechnique Fédérale de LausanneLausanneSwitzerland
  2. 2.Amazon Web ServicesPalo AltoUSA
  3. 3.RAW LabsLausanneSwitzerland
  4. 4.IBM Almaden Research CenterSan JoseUSA

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