Sidewall roughness control in advanced silicon etch process
- Cite this article as:
- Liu, H., Lin, Y. & Hsu, W. Microsystem Technologies (2003) 10: 29. doi:10.1007/s00542-003-0309-8
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In ICP-RIE process, there have been many investigations on etching rate. However, only few published reports mentioned the sidewall roughness, which is a critical issue for optical devices. Here, experimental investigations about fabrication parameters in the STS advanced silicon etch (ASE) process for sidewall roughness are performed. In our experiments, several parameters in the ASE process like over time, ramping time, Ar flow rate, platen power, and etching cycle time have been systematically studied. It is found that sidewall mean roughness can be down to 9.11 nm at etching rate of 2.5 μm/min. Comparing with other published works at similar sidewall roughness (around 10 nm), our experimental data have the highest silicon etching rate. For the same STS ICP-RIE systems, our data have smallest sidewall roughness, comparing to previous data published in the litherature.