Computer Science - Research and Development

, Volume 25, Issue 3, pp 149–154

QPACE: power-efficient parallel architecture based on IBM PowerXCell 8i

Authors

  • H. Baier
    • IBM Deutschland Research & Development GmbH
  • H. Boettiger
    • IBM Deutschland Research & Development GmbH
  • M. Drochner
    • Research Center Jülich
  • N. Eicker
    • Research Center Jülich
    • University of Wuppertal
  • U. Fischer
    • IBM Deutschland Research & Development GmbH
  • Z. Fodor
    • University of Wuppertal
  • A. Frommer
    • University of Wuppertal
  • C. Gomez
    • IBM La Gaude
  • G. Goldrian
    • IBM Deutschland Research & Development GmbH
  • S. Heybrock
    • Department of PhysicsUniversity of Regensburg
  • D. Hierl
    • Department of PhysicsUniversity of Regensburg
  • M. Hüsken
    • University of Wuppertal
  • T. Huth
    • IBM Deutschland Research & Development GmbH
  • B. Krill
    • IBM Deutschland Research & Development GmbH
  • J. Lauritsen
    • IBM Deutschland Research & Development GmbH
  • T. Lippert
    • Research Center Jülich
    • University of Wuppertal
  • T. Maurer
    • Department of PhysicsUniversity of Regensburg
  • B. Mendl
    • Department of PhysicsUniversity of Regensburg
  • N. Meyer
    • Department of PhysicsUniversity of Regensburg
  • A. Nobile
    • Department of PhysicsUniversity of Regensburg
  • I. Ouda
    • IBM Rochester
  • M. Pivanti
    • University of Ferrara
    • Deutsches Elektronen Synchrotron (DESY)
  • M. Ries
    • IBM Deutschland Research & Development GmbH
  • A. Schäfer
    • Department of PhysicsUniversity of Regensburg
  • H. Schick
    • IBM Deutschland Research & Development GmbH
  • F. Schifano
    • University of Ferrara
  • H. Simma
    • Deutsches Elektronen Synchrotron (DESY)
  • S. Solbrig
    • Department of PhysicsUniversity of Regensburg
  • T. Streuer
    • Department of PhysicsUniversity of Regensburg
  • K.-H. Sulanke
    • Deutsches Elektronen Synchrotron (DESY)
  • R. Tripiccione
    • University of Ferrara
  • J.-S. Vogt
    • IBM Deutschland Research & Development GmbH
  • T. Wettig
    • Department of PhysicsUniversity of Regensburg
  • F. Winter
    • Department of PhysicsUniversity of Regensburg
    • Deutsches Elektronen Synchrotron (DESY)
Special Issue Paper

DOI: 10.1007/s00450-010-0122-4

Cite this article as:
Baier, H., Boettiger, H., Drochner, M. et al. Comput Sci Res Dev (2010) 25: 149. doi:10.1007/s00450-010-0122-4

Abstract

QPACE is a novel massively parallel architecture optimized for lattice QCD simulations. Each node comprises an IBM PowerXCell 8i processor. The nodes are interconnected by a custom 3-dimensional torus network implemented on an FPGA. The architecture was systematically optimized with respect to power consumption. This put QPACE in the number one spot on the Green500 List published in November 2009. In this paper we give an overview of the architecture and highlight the steps taken to improve power efficiency.

Keywords

Parallel architecturesSpecial-purpose and application-based systems

Copyright information

© Springer-Verlag 2010