Applied Physics A

, Volume 95, Issue 4, pp 1045–1057

Hybrid silicon evanescent approach to optical interconnects

  • Di Liang
  • Alexander W. Fang
  • Hui-Wen Chen
  • Matthew N. Sysak
  • Brian R. Koch
  • Erica Lively
  • Omri Raday
  • Ying-Hao Kuo
  • Richard Jones
  • John E. Bowers
Open Access
Article

DOI: 10.1007/s00339-009-5118-1

Cite this article as:
Liang, D., Fang, A.W., Chen, HW. et al. Appl. Phys. A (2009) 95: 1045. doi:10.1007/s00339-009-5118-1

Abstract

We discuss the recently developed hybrid silicon evanescent platform (HSEP), and its application as a promising candidate for optical interconnects in silicon. A number of key discrete components and a wafer-scale integration process are reviewed. The motivation behind this work is to realize silicon-based photonic integrated circuits possessing unique advantages of III–V materials and silicon-on-insulator waveguides simultaneously through a complementary metal-oxide semiconductor fabrication process. Electrically pumped hybrid silicon distributed feedback and distributed Bragg reflector lasers with integrated hybrid silicon photodetectors are demonstrated coupled to SOI waveguides, serving as the reliable on-chip single-frequency light sources. For the external signal processing, Mach–Zehnder interferometer modulators are demonstrated, showing a resistance-capacitance-limited, 3 dB electrical bandwidth up to 8 GHz and a modulation efficiency of 1.5 V mm. The successful implementation of quantum well intermixing technique opens up the possibility to realize multiple III–V bandgaps in this platform. Sampled grating DBR devices integrated with electroabsorption modulators (EAM) are fabricated, where the bandgaps in gain, mirror, and EAM regions are 1520, 1440 and 1480 nm, respectively. The high-temperature operation characteristics of the HSEP are studied experimentally and theoretically. An overall characteristic temperature (T0) of 51°C, an above threshold characteristic temperature (T1) of 100°C, and a thermal impedance (ZT) of 41.8°C/W, which agrees with the theoretical prediction of 43.5°C/W, are extracted from the Fabry–Perot devices. Scaling this platform to larger dimensions is demonstrated up to 150 mm wafer diameter. A vertical outgassing channel design is developed to accomplish high-quality III–V epitaxial transfer to silicon in a timely and dimension-independent fashion.

PACS

71.20.Mq 71.55.Eq 42.79.Ta 42.55.Px 
Download to read the full article text

Copyright information

© The Author(s) 2009

Authors and Affiliations

  • Di Liang
    • 1
  • Alexander W. Fang
    • 1
  • Hui-Wen Chen
    • 1
  • Matthew N. Sysak
    • 2
  • Brian R. Koch
    • 1
  • Erica Lively
    • 1
  • Omri Raday
    • 3
  • Ying-Hao Kuo
    • 1
  • Richard Jones
    • 2
  • John E. Bowers
    • 1
  1. 1.Department of Electrical and Computer EngineeringUniversity of CaliforniaSanta BarbaraUSA
  2. 2.Intel CorporationSanta ClaraUSA
  3. 3.Intel CorporationJerusalemIsrael

Personalised recommendations