Theory of Computing Systems

, Volume 48, Issue 1, pp 150–169

Parallelizing Time with Polynomial Circuits

Authors

Article

DOI: 10.1007/s00224-009-9237-z

Cite this article as:
Williams, R. Theory Comput Syst (2011) 48: 150. doi:10.1007/s00224-009-9237-z
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Abstract

We study the problem of asymptotically reducing the runtime of serial computations with circuits of polynomial size. We give an algorithmic size-depth tradeoff for parallelizing time t random access Turing machines, a model at least as powerful as logarithmic cost RAMs. Our parallel simulation yields logspace-uniform tO(1) size, O(t/log t)-depth Boolean circuits having semi-unbounded fan-in gates. In fact, for appropriate d, uniform tO(1)2O(t/d) size circuits of depth O(d) can simulate time t. One corollary is that every log-cost time t RAM can be simulated by a log-cost CRCW PRAM using tO(1) processors and O(t/log t) time. This improves over previous parallel speedups, which only guaranteed an Ω(log t)-speedup with an exponential number of processors for weaker models of computation. These results are obtained by generalizing the well-known result that \(\textsf{DTIME}[t]\subseteq \textsf{ASPACE}[\log t]\).

Keywords

Circuit complexityAlternationParallel speedup

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© Springer Science+Business Media, LLC 2009