Design and Evaluation of CNFET-Based Quaternary Circuits
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DOI: 10.1007/s00034-012-9413-2
- Cite this article as:
- Moaiyeri, M.H., Navi, K. & Hashemipour, O. Circuits Syst Signal Process (2012) 31: 1631. doi:10.1007/s00034-012-9413-2
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Abstract
This paper presents novel high-performance and PVT tolerant quaternary logic circuits as well as efficient quaternary arithmetic circuits for nanoelectronics. These Carbon Nanotube FET (CNFET)-based circuits are compatible with the recent technologies and are designed based on the conventional CMOS architecture, while the previous quaternary designs used methods which are not suitable for nanoelectronics and have become obsolete. The proposed designs are robust and have large noise margins and high driving capability. The singular characteristics of CNFETs, such as the capability of having the desired threshold voltage by regulating the diameters of the nanotubes, make them very appropriate for voltage-mode multiple-threshold circuits design. The proposed circuits are examined, using Synopsys HSPICE with the standard 32 nm-CNFET technology in various situations and different supply voltages. Simulation results demonstrate the correct and high-performance operation of the proposed circuits even in the presence of process, voltage and temperature variations.
Keywords
Carbon nanotube FET (CNFET)Quaternary logicArithmetic and logic circuitsMultiple-V_{th} designNanoelectronics1 Introduction
The present level of sophistication and application of the binary (two-valued) logic is reached mainly on account of the inherent two-state switching behavior of the efficient microelectronic devices. In addition, many powerful arithmetical components and tools have already supported the binary logic to reach its present status. However, the main problems in the binary integrated circuits of the present time are on-chip and off-chip (pin-out) interconnection problems. The first problem causes difficulties in placement and routing of the logic elements and also very large silicon area used for the interconnections. In addition, the second problem restricts the number of connections of an integrated circuit with the external world and is critical in the packaging process. Moreover, implementing many complex applications such as estimation and analysis procedures, process control and decision systems are not either advantageous or even feasible in binary logic. To overcome these physical and electrical problems, digital systems with radices greater than two and accordingly multiple-valued logic (MVL) should be considered. MVL systems permit more than two levels of logic and depending on the number of permitted logic levels, ternary (three-valued) or quaternary (four-valued) logic systems can be considered. It is worth mentioning that the quaternary logic takes advantage of simple conversion between quaternary signals and binary signals, generated by the existing binary circuits. Using MVL instead of binary logic raises the information content per interconnection which results in saving in the number of interconnection wires and in the insulation between them. Furthermore, pins carry more information which results in saving in the number of pins. In addition, it leads to chips with less complexity, more density, more data processing capabilities per unit area and very high-bandwidth serial and parallel data transfer [7, 9, 24]. From the mathematical aspect, redundant and residue number systems permit to decrease or eliminate the rippling carries resulting in more high-speed arithmetic operations than normal binary logic [7]. MVL can be even utilized to resolve the binary problems more efficiently. For example, a third logic value can be used as a medium for signaling the faulty operation in testing the binary circuits [7]. The most common and energy-efficient method for designing MVL circuits is CMOS voltage-mode multiple-threshold (multiple-V_{th}) design [17]. However, it leads to very complex and high-cost fabrication and in some cases becomes impossible, mainly because of requiring depletion-type devices, multilevel ion implantation process technology, extra fabrication steps and multiple precise bias voltages to realize multiple-threshold voltages in MOS transistors. Besides, by the inescapable scaling down the feature size of the MOS transistor deeper in nanoranges, the CMOS technology meets many critical challenges and problems. These difficulties such as reduced gate control, large parametric variations, high power density and high lithography costs restricts the continuous dimension scaling of the MOSFET and decreases its suitability for the near future energy-efficient and robust applications. To overcome these problems, some beyond-CMOS nanodevices such as Quantum-dot Cellular Automata (QCA), Single Electron Transistor (SET) and Carbon Nanotube Field Effect Transistor (CNFET) have been introduced as the potential alternatives for the bulk MOSFET in the time to come [11, 19, 32]. Nevertheless, among these emerging nanotechnologies, CNFET seems to be more appropriate on account of its likeness with MOSFET in terms of inherent electrical properties and consequently many of the previously designed CMOS structures are applicable in CNFET technology without any significant modifications. Moreover, the unique one-dimensional band structure of the CNFET represses backscattering and causes near-ballistic operation, which results in very high-speed operation [19]. CNFET has very high carrier velocity and higher transconductance and consequently has very higher speed and lower power consumption compared to MOSFET. Besides these benefits, CNFET seems to be very promising for overcoming the mentioned problems facing MOSFET in designing MVL circuits. This is due to the fact that the most prevalent and suitable method for designing voltage-mode MVL circuits is the multiple-V_{th} design technique and the desired threshold voltage can be obtained by adopting proper diameter for the nanotubes of the CNFET device [10, 17, 19, 27].
Several types of MVL circuit, specifically ternary, have already been presented in the literature since the emerging of MOSFET technology [2, 3, 8, 21, 22, 30, 31, 33, 34, 36]. Nevertheless, they suffer from many drawbacks which significantly degrade their suitability for the recent and the near future technologies. For instance designs of [21, 22] use large resistors, designs of [3, 8, 21, 22, 31, 33] require multiple supply voltages and designs of [2, 3, 8, 33, 34, 36] use depletion-mode MOSFETs which have become obsolete. Furthermore, in the recent years, some state-of-the-art CNFET-based ternary circuits have been proposed in the literature which benefit from the unique properties of carbon nanotube transistors [10, 15, 17, 19, 27]. However, limited efforts have been made so far for developing efficient MVL circuits for radices greater than three mostly due to technology concerns and hardware inefficiencies. Notwithstanding the mentioned advantages of MVL, from the hardware implementation point of view, MVL designs must be compatible with the existing inherently binary technologies. In this paper new CNFET-based robust and energy-efficient quaternary logic gates, decoder, multiplexer and arithmetic circuits are proposed. In the remainder of the paper, Sect. 2 briefly reviews the CNFET device. The new CNFET-based MVL circuits are presented in Sect. 3. The functionality, performance and immunity to process variation of the proposed circuits are evaluated in Sect. 4 and finally, Sect. 5 concludes the paper.
2 Review of Carbon Nanotube Field Effect Transistors (CNFETs)
The transistor sizing process of CNFET-based designs is less complex in comparison with the MOSFET-based designs, specifically for larger and more intricate circuits. This is due to the fact that contrary to MOSFET, electrons and holes have same mobilities in CNT (μ_{n}=μ_{p}) [1]. Ballistic conduction as well as the one-dimensional structure of CNT decrease the resistivity and significantly enhances the speed and minimize the energy dissipation of the device and reduce the power consumption density in the channel of CNFET.
Three distinct types of CNFET have been introduced so far in the literature, i.e. SB-CNFET, T-CNFET and MOSFET-like CNFET [28]. However, considering these kinds of CNFET, MOSFET-like CNFET is more appropriate for designing circuits based on the CMOS platform, on account of more resemblance with MOSFET in terms inherent electrical characteristics and transistor structure.
In addition, in [26, 37], fabrication of VLSI-compatible and imperfection-immune combinational and sequential CNFET logic circuits has been reported. These logic circuits, such as half-adder sum generators and D-latches, are the fundamental building blocks of VLSI digital systems. Chemical doping of CNTs to fabricate and integrate p-type and n-type CNFETs on the same substrate is also an important area of future research in order to reach complementary VLSI CNFET circuits [26].
In this work, we utilize multidiameter complimentary CNFET-based design method [17, 19] for designing the proposed quaternary logic circuits.
3 The Proposed Quaternary Circuits
3.1 Quaternary Logic Gates
This quaternary buffer has a different design style with respect to the previously presented quaternary structures and is designed based on binary inverters. In addition, according to Fig. 3(b) the proposed QBuffer has a near-ideal VTC with high gain and very high-steep transition regions which leads to larger noise margins and lower power consumption. As a result, the proposed circuit is more robust and more suitable for low-voltage applications, compared to the previous structures. This high-precision quaternary buffer can be utilized as a driving booster or a voltage level restorer in larger quaternary circuits. In the proposed quaternary buffer, the transition points of the binary inverters are specified by setting proper threshold voltages for their CNFETs, which are determined by the diameter of their CNTs [10, 17, 19, 27], according to Eq. (2). In this design, for CNFETs with diameters of 2.27 nm, 1.487 nm and 0.783 nm, the chirality numbers would be (29,0), (19,0) and (10,0) and consequently, the threshold voltage values (|V_{th}|) would be 0.192 V, 0.293 V and 0.557 V, respectively. Furthermore, the transition regions can be tuned by adopting proper number of nanotubes for the CNFETs. According to Fig. 3, the operation of the proposed CNFET-based quaternary buffer can be briefly described as follows: when the input voltage is around 0 V or V_{DD}, T_{2} and T_{4} or T_{1} and T_{3} are ON and the output voltage would be 0 V or V_{DD}, respectively. Moreover, if the input voltage reaches around \(\frac{1}{3}V_{\mathrm{DD}}\) or \(\frac{2}{3}V_{\mathrm{DD}}\), T_{1}, T_{2} and T_{4} or T_{1}, T_{2} and T_{3} are ON and the output voltage would be \(\frac{1}{3}V_{\mathrm{DD}}\) or \(\frac{2}{3}V_{\mathrm{DD}}\), respectively, according to the voltage division between these CNFETs, which work in the linear region.
It is worth mentioning that for designing the proposed quaternary CNFET-based circuits only three different diameters are used for the nanotubes, while this number of diameters has been used in the previous works for designing ternary logic circuits [15, 17, 19].
It is worth mentioning that although the threshold voltage of the nano-MOSFET can also be varied, it cannot be used to design the proposed quaternary circuits with L_{g}=32 nm at 32 nm technology node, due to the very lower gain of the MOSFET-based binary inverters, in the transition region, compared to their CNFET-based counterparts [1], which is not adequate for this application. However, the gain of the input binary inverters is a very determining factor for correct operation, precision and robustness of the proposed quaternary designs, as shown in Figs. 4 and 5. To make the MOSFETs applicable for designing the proposed quaternary circuits, the gain of the binary inverters should becomes considerably higher, by increasing the channel length of the MOSFETs, which results in significant speed degradation and more area wastage, in comparison with the CNFET-based designs. Nevertheless, the gain of the binary inverters is still lower than their CNFET counterparts. In Sect. 4, the proposed CNFET-based quaternary circuits are compared with their MOSFET-based equivalents in terms of performance and energy efficiency.
3.2 Basic Quaternary Arithmetic Circuits
Truth table of quaternary half adder and one-digit multiplier
Input | Output (quaternary HA) | Output (quaternary multiplier) | |||
---|---|---|---|---|---|
A | B | QSUM | QCarry | QProduct | QCarry |
0 | 0 | 0 | 0 | 0 | 0 |
0 | 1 | 1 | 0 | 0 | 0 |
0 | 2 | 2 | 0 | 0 | 0 |
0 | 3 | 3 | 0 | 0 | 0 |
1 | 0 | 1 | 0 | 0 | 0 |
1 | 1 | 2 | 0 | 1 | 0 |
1 | 2 | 3 | 0 | 2 | 0 |
1 | 3 | 0 | 1 | 3 | 0 |
2 | 0 | 2 | 0 | 0 | 0 |
2 | 1 | 3 | 0 | 2 | 0 |
2 | 2 | 0 | 1 | 0 | 1 |
2 | 3 | 1 | 1 | 2 | 1 |
3 | 0 | 3 | 0 | 0 | 0 |
3 | 1 | 0 | 1 | 3 | 0 |
3 | 2 | 1 | 1 | 2 | 1 |
3 | 3 | 2 | 1 | 1 | 2 |
A gate-level method, such as the one proposed in [17] for ternary logic, can be used for designing the quaternary basic arithmetic circuits based on the following equations, derived from Table 1.
However, this method is not efficient at all for designing quaternary arithmetic circuits and leads to a large number of logic gates and consequently a very large number of transistors. Another method is the multiplexer (MUX) logic design. Nevertheless, the efficiency of this method significantly depends on the hardware efficiency of the quaternary multiplexer. A quaternary four-to-one multiplexer has been proposed in [3], based on the quaternary logic gates. However, using this gate-level quaternary multiplexer for designing the quaternary arithmetic circuits is not efficient and leads to a very large number of transistors as well as a longer critical path.
It should be noted that the inverters of the quaternary decoder operate based on the VTCs, shown in Fig. 3(b) (NOT1, NOT2 and NOT3), and the NOR circuits are conventional CMOS-style two-input NOR gates with symmetrical VTCs.
It is worth noting that for designing the proposed quaternary CNFET-based arithmetic circuits only three different diameters are used for the nanotubes, whereas this number of diameters has been used in the previous works for designing the simple ternary logic gates [15, 17, 19].
4 Simulation Results
Characteristics of the used MOSFET-like CNFET model
Parameter | Brief description | Value |
---|---|---|
L_{ch} | Physical channel length | 32 nm |
L_{ss} | The length of doped CNT source-side extension region | 32 nm |
L_{dd} | The length of doped CNT drain-side extension region | 32 nm |
L_{geff} | The Scattering mean free path in the intrinsic CNT channel and S/D regions | 100 nm |
Pitch | The distance between the centers of two neighboring CNTs within the same device | 20 nm |
L_{eff} | The mean free path in p+/n+ doped CNT. | 15 nm |
sub_pitch | Sub-lithographic (e.g. CNT gate width) pitch | 4 nm |
K_{ox} | The dielectric constant of high-k top gate dielectric material (HfO_{2}) | 16 |
T_{ox} | The thickness of high-k top gate dielectric material | 4 nm |
K_{sub} | The dielectric constant of substrate (SiO_{2}) | 4 |
C_{sub} | The coupling capacitance between the channel region and the substrate (SiO_{2}) | 40 aF/μm |
Efi | The Fermi level of the doped S/D tube | 6 eV |
phi_M | The work function of Source/Drain metal contact | 4.6 eV |
phi_S | CNT work function | 4.5 eV |
Simulation results of the proposed quaternary logic gates
V_{DD} (V) | 0.8 V | 0.9 V | 1 V |
---|---|---|---|
Delay (×10^{−12} s) | |||
CNFET | |||
QBuffer | 3.3999 | 2.9695 | 2.9134 |
QNOT | 4.4315 | 3.0603 | 2.9412 |
Two-input QMIN | 8.9671 | 7.0831 | 7.5787 |
Two-input QMAX | 7.5766 | 7.0552 | 7.1490 |
Three-input QMIN | 15.512 | 12.148 | 12.136 |
Three-input QMAX | 12.145 | 11.995 | 11.037 |
MOSFET | |||
QBuffer | 45.413 | 32.612 | 26.222 |
QNOT | 50.298 | 38.787 | 33.071 |
Two-input QMIN | 92.595 | 69.978 | 57.650 |
Two-input QMAX | 132.31 | 98.649 | 81.909 |
Three-input QMIN | 115.38 | 90.829 | 83.279 |
Three-input QMAX | 151.09 | 120.97 | 120.12 |
Power (×10^{−5} W) | |||
CNFET | |||
QBuffer | 1.8306 | 2.4260 | 3.1291 |
QNOT | 1.8339 | 2.4306 | 3.1588 |
Two-input QMIN | 2.0668 | 2.7381 | 3.5507 |
Two-input QMAX | 2.0677 | 2.7398 | 3.5550 |
Three-input QMIN | 2.1559 | 2.8441 | 3.7408 |
Three-input QMAX | 2.1735 | 2.8819 | 3.7233 |
MOSFET | |||
QBuffer | 2.7027 | 3.6700 | 4.8407 |
QNOT | 2.6739 | 3.6363 | 4.8099 |
Two-input QMIN | 3.2328 | 4.3898 | 5.7571 |
Two-input QMAX | 2.7875 | 3.7925 | 4.9911 |
Three-input QMIN | 3.5845 | 4.866 | 6.3565 |
Three-input QMAX | 2.8917 | 3.9631 | 5.3068 |
Energy Consumption (×10^{−16} J) | |||
CNFET | |||
QBuffer | 0.6224 | 0.7204 | 0.9116 |
QNOT | 0.8127 | 0.7438 | 0.9291 |
Two-input QMIN | 1.8533 | 1.9394 | 2.6909 |
Two-input QMAX | 1.5665 | 1.9329 | 2.5414 |
Three-input QMIN | 3.3442 | 3.4550 | 4.5398 |
Three-input QMAX | 2.6397 | 3.4568 | 4.1094 |
MOSFET | |||
QBuffer | 12.274 | 11.969 | 12.693 |
QNOT | 13.449 | 14.104 | 15.907 |
Two-input QMIN | 29.934 | 30.719 | 33.189 |
Two-input QMAX | 36.881 | 37.413 | 40.882 |
Three-input QMIN | 41.358 | 44.197 | 52.936 |
Three-input QMAX | 43.691 | 47.942 | 63.745 |
Systematic and random process variations are among the most significant challenges ahead of designing the nanoscale devices and circuits. As the presented CNFET-based quaternary logic circuits are designed based on multiple-V_{th} method, the impact of the process variations, which alternate the threshold voltages of the CNFETs, should be definitely studied. The most important parameters which determine the threshold voltage value of a CNFET are the diameter of its nanotubes and the thickness of its gate oxide layer (T_{ox}). Inasmuch as the timing variation is considered as a very important characteristic for a circuit, delay characteristics together with the energy consumption of the proposed circuits are investigated in the presence of process variation.
It is worth noting that the delay of the proposed quaternary logic circuits experience considerably less variation in the presence of process variation even compared with the state-of-the-art CNFET-based ternary logic circuits presented in the literature [15, 17].
Simulation results of CNFET-based quaternary arithmetic circuits
V_{DD} (V) | 0.8 V | 0.9 V | 1 V |
---|---|---|---|
Quaternary half adder | |||
Delay (×10^{−12} s) | |||
Proposed design | 24.219 | 20.573 | 18.916 |
Design based on [17] | 45.408 | 38.336 | 34.486 |
Design based on [3] | 54.914 | 46.142 | 34.486 |
Power (×10^{−5} W) | |||
Proposed design | 0.2294 | 0.5882 | 1.2714 |
Design based on [17] | 4.6469 | 6.3687 | 8.6289 |
Design based on [3] | 39.195 | 52.067 | 86.289 |
Energy Consumption (×10^{−16} J) | |||
Proposed design | 0.5555 | 1.2101 | 2.4049 |
Design based on [17] | 21.101 | 24.415 | 29.758 |
Design based on [3] | 215.23 | 240.24 | 297.58 |
Quaternary one-digit multiplier | |||
Delay (×10^{−12} s) | |||
Proposed design | 25.745 | 21.928 | 20.059 |
Design based on [17] | 33.738 | 27.580 | 25.719 |
Design based on [3] | 44.055 | 33.005 | 28.865 |
Power (×10^{−5} W) | |||
Proposed design | 0.2164 | 0.5379 | 1.1292 |
Design based on [17] | 5.1108 | 6.9856 | 9.4342 |
Design based on [3] | 27.845 | 37.056 | 48.366 |
Energy Consumption (×10^{−16} J) | |||
Proposed design | 0.5573 | 1.1795 | 2.2651 |
Design based on [17] | 17.243 | 19.267 | 24.263 |
Design based on [3] | 122.67 | 122.3 | 139.61 |
5 Conclusion
New high-speed, high-precision and PVT tolerant quaternary logic gates, decoder, multiplexer and arithmetic circuits have been proposed for nanotechnology, based on CNFETs. The proposed CNFET-based circuits have been designed based on the CMOS-style binary gates, composed of multiple-V_{th} nanodevices, and have benefited from the unique properties of CNFET. Moreover, the proposed MVL designs are compatible with the recent technologies. For designing the proposed quaternary circuits only three different CNT diameters, all less than 2.3 nm, have been used which enhance the feasibility and manufacturability of the designs. The simulation results confirm the authenticity of the proposed method in various simulation conditions as well as in the presence of process, voltage and temperature variations.