New Generation Computing

, Volume 3, Issue 3, pp 307–328

A VLSI algorithm for sorting variable-length character strings

  • Yuzuru Tanaka
Regular Papers

DOI: 10.1007/BF03037124

Cite this article as:
Tanaka, Y. New Gener Comput (1985) 3: 307. doi:10.1007/BF03037124

Abstract

This paper proposes a sorting hardware module that can directly cope with variable length character strings. It gives a pipelined heap sort algorithm for a set of variable-length character strings, and a VLSI architecture that implements this algorithm. The hardware consists of a specially designed single chip module and an external memory bank. This special chip module is called a V-Sort Engine Core. The number of words in the external memory bank should be larger than the total length of strings to be sorted. A hardware module that can sort no more than 2L strings uses a V-Sort Engine core consisting ofL levels. Thei-th level of a V-Sort Engine Core has a logic cell and a memory bank with 2i words. Each word consists of three fields and a mark bit, i. e., level number, character, and path number. A triple (j, c, i) consisting of these field values denotes thej+1st characterc of thei-th input string. Concurrent execution of the external memory bank and all the level logic cells of the V-Sort Engine Core allows the hardware module to receive a sequence of strings sequentially character by character, and to begin the sequential output of the sort result immediately after receiving the last input character. It requires no extra time other than those required for sequential data transfer to and from itself.

Keywords

SortingCharacter String ProcessingParallel ProcessingVLSI Algorithm

Copyright information

© Ohmsha, Ltd. and Springer 1985

Authors and Affiliations

  • Yuzuru Tanaka
    • 1
  1. 1.Department of Electrical EngineeringHokkaido UniversitySapporoJapan