Journal of Computer Science and Technology

, Volume 17, Issue 6, pp 718–730

Lower bound estimation of hardware resources for scheduling in high-level synthesis

  • Shen Zhaoxuan 
  • Jong Ching Chuen 
Regular Papers

DOI: 10.1007/BF02960762

Cite this article as:
Shen, Z. & Jong, C.C. J. Compt. Sci. & Technol. (2002) 17: 718. doi:10.1007/BF02960762


In high-level synthesis of VLSI circuits, good lower bound prediction can efficiently narrow down the large space of possible designs. Previous approaches predict the lower bound by relaxing or even ignoring the precedence constraints of the data flow graph (DFG), and result in inaccuracy of the lower bound. The loop folding and conditional branch were also not considered. In this paper, a new stepwise refinement algorithm is proposed, which takes consideration of precedence constraints of the DFG to estimate the lower bound of hardware resources under time constraints. Processing techniques to handle multi-cycle, chaining, pipelining, as well as loop folding and mutual exclusion among conditional branches are also incorporated in the algorithm. Experimental results show that the algorithm can produce a very tight and close to optimal lower bound in reasonable computation time.


lower bound estimationchainingpipeliningmutual exclusionhigh-level synthesis

Copyright information

© Science Press, Beijing China and Allerton Press Inc. 2002

Authors and Affiliations

  • Shen Zhaoxuan 
    • 1
  • Jong Ching Chuen 
    • 1
  1. 1.School of Electrical and Electronic EngineeringNanyang Technological UniversitySingapore