, Volume 15, Issue 1, pp 84-95

Timing-sequence testing of parallel programs

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Abstract

Testing of parallel programs involves two parts—testing of control-flow within the processes and testing of timing-sequence. This paper focuses on the latter, particularly on the timing-sequence of message-passing paradigms. Firstly the coarse-grained SYN-sequence model is built up to describe the execution of distributed programs. All of the topics discussed in this paper are based on it. The most direct way to test a program is to run it. A fault-free parallel program should be of both correct computing results and proper SYN-sequence. In order to analyze the validity of observed SYN-sequence, this paper presents the formal specification (Backus Normal Form) of the valid SYN-sequence. Till now there is little work about the testing coverage for distributed programs. Calculating the number of the valid SYN-sequences is the key to coverage problem, while the number of the valid SYN-sequences is terribly large and it is very hard to obtain the combination law among SYN-events. In order to resolve this problem, this paper proposes an efficient testing strategy—atomic SYN-event testing, which is to linearize the SYN-sequence (making it only consist of serial atomic SYN-events) first and then test each atomic SYN-event independently. This paper particularly provides the calculating formula about the number of the valid SYN-sequences for tree-topology atomic SYN-event (broadcast and combine). Furthermore, the number of valid SYN-sequences also, to some degree, mirrors the testability of parallel programs. Taking tree-topology atomic SYN-event as an example, this paper demonstrates the testability and communication speed of the tree-topology atomic SYN-event under different numbers of branches in order to achieve a more satisfactory tradeoff between testability and communication efficiency.

This work was supported by the National Natural Science Foundation of China under Grant No.69896250.
LIANG Yu received his B.Eng. degree from Tsinghua University in 1990 and M.Eng degree from Beijing Polytechnic University in 1995. He is currently studying in the Institute of Computing Technology, Chinese Academy of Sciences as a Ph.D. candidate. His research interests include high performance computer architecture, fault-tolerance & testing technology and parallel computing.
LI Shu received his B.Eng. degree from Tongji University in 1996. He is currently studying in the Institute of Computing Technology, Chinese Academy of Sciences as a Ph.D. candidate. His research interests include fast transforms in signal processing and parallel processing.
ZHANG Hui received his B.Eng. degree from Shanghai JiaoTong University in 1995. He is currently studying in the Institute of Computing Technology, Chinese Academy of Sciences as a Master student. His research interests include high performance computer architecture, image processing and computer network.
HAN Chengde is a Research Professor of the Institute of Computing Technology, Chinese Academy of Sciences. His research interests include high performance computer architecture, signal processing and geographical information system.