Algorithmica

, Volume 2, Issue 1, pp 113–129

Global wire routing in two-dimensional arrays

  • R. M. Karp
  • F. T. Leighton
  • R. L. Rivest
  • C. D. Thompson
  • U. V. Vazirani
  • V. V. Vazirani
Article

DOI: 10.1007/BF01840353

Cite this article as:
Karp, R.M., Leighton, F.T., Rivest, R.L. et al. Algorithmica (1987) 2: 113. doi:10.1007/BF01840353

Abstract

We examine the problem of routing wires of a VLSI chip, where the pins to be connected are arranged in a regular rectangular array. We obtain tight bounds for the worst-case “channel-width” needed to route ann×n array, and develop provably good heuristics for the general case. Single-turn routings are proved to be near-optimal in the worst-case.

A central result of our paper is a “rounding algorithm” for obtaining integral approximations to solutions of linear equations. Given a matrix A and a real vector x, then we can find an integral x such that for alli, ¦xi-xi¦ <1 and (Ax)i-(Ax)i<Δ. Our error bound Δ is defined in terms of sign-segregated column sums of A:
$$\Delta = \mathop {\max }\limits_j \left( {\max \left\{ {\sum\limits_{i:a_{ij} > 0} {a_{ij} ,} \sum\limits_{i:a_{ij}< 0} { - a_{ij} } } \right\}} \right).$$

Key words

Global routingGate arraysInteger programmingLinear programmingComputer-aided design for integrated circuits

Copyright information

© Springer-Verlag New York Inc. 1987

Authors and Affiliations

  • R. M. Karp
    • 1
  • F. T. Leighton
    • 2
  • R. L. Rivest
    • 2
  • C. D. Thompson
    • 1
  • U. V. Vazirani
    • 1
  • V. V. Vazirani
    • 3
  1. 1.Computer Science DivisionUniversity of CaliforniaBerkeleyUSA
  2. 2.Mathematics Department and Laboratory for Computer ScienceMassachusetts Institute of TechnologyCambridgeUSA
  3. 3.Computer Science DepartmentCornell UniversityIthacaUSA