Formal Methods in System Design

, Volume 6, Issue 2, pp 217–232

Verification of the Futurebus+ cache coherence protocol

Authors

  • Edmund M. Clarke
    • School of Computer ScienceCarnegie Mellon University
  • Orna Grumberg
    • Computer Science DepartmentThe Technion
  • Hiromi Hiraishi
    • Department of Information and Communication SciencesKyoto Sangyo University
  • Somesh Jha
    • School of Computer ScienceCarnegie Mellon University
  • David E. Long
    • School of Computer ScienceCarnegie Mellon University
  • Kenneth L. McMillan
    • School of Computer ScienceCarnegie Mellon University
  • Linda A. Ness
Article

DOI: 10.1007/BF01383968

Cite this article as:
Clarke, E.M., Grumberg, O., Hiraishi, H. et al. Form Method Syst Des (1995) 6: 217. doi:10.1007/BF01383968

Abstract

We used a hardware description language to construct a formal model of the cache coherence protocol described in the IEEE Futurebus+standard. By applying temporal logic model checking techniques, we found errors in the standard. The result of our project is a concise, comprehensible and unambiguous model of the protocol that should be useful both to the Futurebus+Working Group members, who are responsible for the protocol, and to actual designers of Futurebus+boards.

Keywords

The computer industry, standards, Futurebus+multiple data stream architectures, interconnection architecturesnetwork protocols, protocol verification

Copyright information

© Kluwer Academic Publishers 1995