Verification of the Futurebus+ cache coherence protocol
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We used a hardware description language to construct a formal model of the cache coherence protocol described in the IEEE Futurebus+standard. By applying temporal logic model checking techniques, we found errors in the standard. The result of our project is a concise, comprehensible and unambiguous model of the protocol that should be useful both to the Futurebus+Working Group members, who are responsible for the protocol, and to actual designers of Futurebus+boards.
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- Verification of the Futurebus+ cache coherence protocol
Formal Methods in System Design
Volume 6, Issue 2 , pp 217-232
- Cover Date
- Print ISSN
- Online ISSN
- Kluwer Academic Publishers
- Additional Links
- The computer industry, standards, Futurebus+
- multiple data stream architectures, interconnection architectures
- network protocols, protocol verification
- Industry Sectors
- Author Affiliations
- 1. School of Computer Science, Carnegie Mellon University, 15213, Pittsburgh, PA, USA
- 2. Computer Science Department, The Technion, 32000, Haifa, Israel
- 4. Department of Information and Communication Sciences, Kyoto Sangyo University, 603, Kyoto, Japan
- 5. School of Computer Science, Carnegie Mellon University, 15213, Pittsburgh, PA, USA
- 6. Bellcore, 07962, Morristown, NJ, USA