Analog Integrated Circuits and Signal Processing

, Volume 8, Issue 3, pp 247–257

An analogue vector matching architecture

Authors

  • S. Collins
    • DRA Malvern
  • D. R. Brown
    • DRA Malvern
  • G. F. Marshall
    • DRA Malvern
Article

DOI: 10.1007/BF01240838

Cite this article as:
Collins, S., Brown, D.R. & Marshall, G.F. Analog Integr Circ Sig Process (1995) 8: 247. doi:10.1007/BF01240838

Abstract

A two transistor analogue circuit is described which exploits the native device characteristics of a MOSFET to calculate the square of the Euclidean distance between two points. Simulations suggest that this circuit can be employed as the basis of a low-power vector matching architecture which could be used for vector quantisation or nearest neighbour classification.

Keywords

floating-gate nearest-neighbour vector quantisation pattern recognition

Copyright information

© Kluwer Academic Publishers, Boston. Manufactured in The Netherlands 1995