Journal of Electronic Testing

, Volume 7, Issue 1, pp 25–46

Partial scan design of register-transfer level circuits

  • Rajesh Gupta
  • Melvin A. Breuer
High-Level Design

DOI: 10.1007/BF00993312

Cite this article as:
Gupta, R. & Breuer, M.A. J Electron Test (1995) 7: 25. doi:10.1007/BF00993312


Register-transfer level designs that are derived from high-level synthesis systems generally consist of functional blocks and registers that are interconnected by multiplexers and buses to maximize resource sharing These multiplexer and bus structures have the unique ability to behave asswitches, i.e., to logically partition the circuit when their control inputs are manipulated in different ways. The presence of switches, the selection of scan registers can be influenced. This leads to an efficient partial scan methodology presented in this paper. Second, switches help set up data transfer paths calledI-paths. By employingI-paths to transport test data, the functional logic in the circuit can be separated from the switching logic for the purpose of test generation. This can lead to a reduction in test generation costs for a partial scan design. Thus the techniques presented in this paper help to minimize both testability overhead and test generation cost in bus-based circuits. This methodology is implemented in the SIESTA system for serial scan design.

Key Words

design for testabilityserial scan designpartial scan designregister-transfer level designsbalanced structuresI-paths

Copyright information

© Kluwer Academic Publishers 1995

Authors and Affiliations

  • Rajesh Gupta
    • 1
  • Melvin A. Breuer
    • 2
  1. 1.IBM MicroelectronicsHopewell Jct.
  2. 2.Department of Electrical Engineering-SystemsUniversity of Southern CaliforniaLos Angeles