CSP-based object-oriented description and simulation of a reconfigurable adaptive beamforming architecture using the OODRA workbench

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Application of the Object-Oriented Design of Reliable/Reconfigurable Architectures (OODRA) workbench to the performance simulation of a reconfigurable adaptive digital beamforming architecture is described in this paper. The performance effects due to chip/wafer partitioning and reconfiguration for fault tolerance and yield enhancement are presented. The experiments described illustrate use of the OODRA workbench in architectural-level performance evaluation of algorithm-specific reconfigurable architectures, particularly for signal processing applications.

This research was supported in part by SDIO/IST and managed by the Office of Naval Research under contract N00014-89-K-0070 and in part by the Semiconductor Research Corporation under Contract 88-DP-109. Portions of this paper were presented at the IEEE International Conference on Wafer Scale Integration, January 1989, and the ACM/IEEE Design Automation Conference, June 1989.