M. Ajtai, L. Babai, P. Hajnal, J. Komlos, P. Pudlak, V. Rödl, E. Szemeredi, and G. Turan, “Two lower bounds for branching programs,”Proc. 18th ACM STOC, 1986, pp. 30–38.
B. Becker, “Synthesis for testability: Binary decision diagrams,”Proc. of 9th Annual Symposium on Theoretical Aspects of Computer Science, Lecture Notes in Computer Science, February 1992, Vol 577, pp. 501–512.
B. Becker and R. Drechsler,On the Computational Power of Functional Decision Diagrams, Interner Bericht 5/93, Universität Frankfurt, 1993.
M.Blum, A.K.Chandra, and M.N.Wegman, “Equivalence of free boolean graphs can be decided probabilistically in polynomial time,”IPL 10
, Vol. 2, pp. 80–82, 1980.MathSciNet
S.D. Brown, R.J. Francis, J. Rose, and Z.G. Vranesic,Field-Programmable Gate Arrays, Kluwer Academic Publisher, 1992.
R.E.Bryant, “Graph-based algorithms for boolean function manipulation,”IEEE Trans. Comput. C-35, Vol. 6, pp. 677–691, August 1986.
R.E.Bryan, “On the complexity of VLSI implementations and graph representations of boolean functions with applications to integer multiplication”,IEEE Trans. Comput. 40
, Vol. 2, pp. 205–213, February 1991.CrossRef
R.E.Bryant, “Symbolic boolean manipulation with ordered binary decision diagrams,”ACM Computing Surveys
, Vol. 24, No. 3, pp. 293–318, September 1992.CrossRef
J.R. Burch, E.M. Clarke, K.L. McMillan, and D.L. Dill, “Sequential circuit verification using symbolic model checking,”Proc. of 27th ACM/IEEE Design Automation Conference, Orlando, June 1990, pp. 46–51.
O. Coudert, J.-C. Madre, and C. Berthet, “Verifying temporal properties of sequential machines without building their state diagrams”,Proc. of Computer-Aided Verification, Rutgers, N.J., June 1990, pp. 75–84.
R. Drechsler and B. Becker,Rapid Prototyping of Fully Testable Multi-Level AND/EXOR Networks, Interner Bericht 4/93, Universität Frankfurt, 1993.
H.Eveking,Verifikation digitaler Systeme, Teubner, Stuttgart, 1991.
J. Gergov and Ch. Meinel, “Frontiers of feasible and probabilistic feasible boolean manipulation with branching programs,”Proc. of 10th Annual Symposium on Theoretical Aspects of Computer Science, (February), Lecture Notes in Computer Science, Vol. 665, 1993, pp. 576–585.
J. Gergov and Ch. Meinel, “Efficient analysis and manipulation of OBDDs can be extended to FBDDs”,IEEE Transactions on Computers, Vol. 43, No. 10, 1994.
J.Jain, J.Bitner, D.S.Fussell, and J.Abraham, “Probabilistic verification of Boolean functions,”Formal Methods in System Design
, Vol. 1, pp. 63–117, 1992.CrossRef
U. Kebschull, E. Shubert, and W. Rosenstiel, “Multilevel logic synthesis based on functional decision diagrams”,Proc. EDAC'92, 1992, pp. 43–47.
R. Lidl and H. Niederreiter,Introduction to Finite Fields and Their Applications, Cambridge University Press, 1986.
S. Malik, A. Wang, and R.K. Brayton, “A. Sangiovanni-Vincentelli: Logic verification using binary decision diagrams in a logic synthesis environment”,Proc. IEEE International Conference on Computer-Aided Design, Santa Clara, Calif., November 1988, pp. 6–9.
Ch. Meinel,Modified Branching Programs and Their Computational Power, Springer Verlag, LNCS 370, 1989.
H. Minato, N. Ishiura, and S. Yajima, “Shared binary decision diagrams with attributed edges for efficient boolean function manipulation”,Proc. 27th ACM/IEEE Design Automation Conference, Orlando, June 1990, pp. 52–57.
D.E.Muller, “Application of Boolean algebra to switching circuit design and to error correction,”IRE Trans. Electr. Comp., Vol. 3, No. 3, pp. 6–12, September 1954.
M.A. Perkowski, L. Csansky, A. Sarabi, and I. Schäfer, “Fast minimization of mixed polarity AND/XOR canonical networks”,Proceedings of ICCD'92, 1992, pp. 33–36.
A.A. Razborov, “A lower bound on the size of bounded depth networks over a complete basis with logical addition”,Mat. Zametki, Vol. 41, No. 4, pp. 598–607, 1987 (in Russian); English translation in:Math. Notes, Vol. 41, No. 4, pp. 333–338, 1987.
S.M.Reddy, “Easily testable realizations for logical functions,”IEEE Trans. Comput.
, Vol. C21, pp. 1183–1188, November 1972.MATH
I.S.Reed, “A class of multiple-error-correcting codes and their decoding scheme,”IRE Trans. Inf. Theory
, Vol. PGIT-4, pp. 38–49, 1954.CrossRef
T.Sasao and Ph.W.Besslich, “On the Complexity of Mod-2 Sum PLAs,”IEEE Trans. Comput.
, Vol. 39, No. 2, pp. 269–266, February 1990.CrossRef
T. Sasao, ”Optimization of multi-valued AND-EXOR expressions using multiple-place decision diagrams”,Proceedings of the 22nd Int. Symp. of Multi-Valued Logic, 1992, pp. 451–458.
J.M. Saul, “Logic synthesis for arithmetic circuits using Reed-Muller representation”,Proc. EDAC'92, March 1992.