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Test quality of hierarchical defect-tolerant integrated circuits

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Abstract

This paper presents a theoretical expression to evaluate the test quality of hierarchical defect-tolerant integrated circuits. This expression, which is developed for circuits with two levels of hierarchy, is based on a defect model with which one can take into account the relative importance (probability of occurrence) of each defect and consequently of each fault. Results obtained from this expression show that, for a given test coverage, the addition of defect-tolerance mechanisms decreases the test quality of integrated circuits. These results are important because they indicate that fault coverage can be a misleading measure of the test quality of defect-tolerant integrated circuits.

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Authors and Affiliations

  1. Electrical Engineering Department, Ecole Polytechnique de Montréal, C.P. 6079, Station A, H3C 3A7, Montreal, QC, Canada

    Yvon Savaria & Jean -Louis Houle

  2. Computer Science Department, U.Q.A.M., C.P. 8888, Station A, H3C 3P8, Montreal, QC, Canada

    Claude Thibeault

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  1. Claude Thibeault
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  2. Yvon Savaria
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  3. Jean -Louis Houle
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Thibeault, C., Savaria, Y. & Houle, J.L. Test quality of hierarchical defect-tolerant integrated circuits. J Electron Test 3, 93–102 (1992). https://doi.org/10.1007/BF00159834

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  • DOI: https://doi.org/10.1007/BF00159834

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