Journal of Electronic Testing

, Volume 1, Issue 2, pp 163–174

An analytical approach to the partial scan problem

  • Arno Kunzmann
  • Hans-Joachim Wunderlich
Design for Testability

DOI: 10.1007/BF00137392

Cite this article as:
Kunzmann, A. & Wunderlich, HJ. J Electron Test (1990) 1: 163. doi:10.1007/BF00137392

Abstract

The scan design is the most widely used technique used to ensure the testability of sequential circuits. In this article it is shown that testability is still guaranteed, even if only a small part of the flipflops is integrated into a scan path. An algorithm is presented for selecting a minimal number of flipflops, which must be directly accessible. The direct accessibility ensures that, for each fault, the necessary test sequence is bounded linearly in the circuit size. Since the underlying problem is NP-complete, efficient heuristics are implemented to compute suboptimal solutions. Moreover, a new algorithm is presented to map a sequential circuit into a minimal combinational one, such that test pattern generation for both circuit representations is equivalent and the fast combinational ATPG methods can be applied. For all benchmark circuits investigated, this approach results in a significant reduction of the hardware overhead, and additionally a complete fault coverage is still obtained. Amazingly the overall test application time decreases in comparison with a complete scan path, since the width of the shifted patterns is shorter, and the number of patterns increase only to a small extent.

Key words

design for testabilitypartial scan pathsequential test generation

Copyright information

© Kluwer Academic Publishers 1990

Authors and Affiliations

  • Arno Kunzmann
    • 1
  • Hans-Joachim Wunderlich
    • 1
  1. 1.Institute of Computer Design and Fault Tolerance, University of KarlsruheKarlsruheF.R. Germany