Journal of Electronic Testing

, Volume 2, Issue 1, pp 77–88

Boundary scan test, test methodology, and fault modeling


  • Frans De Jong
    • Philips, CFT-Automation
  • José S. Matos
    • INESC
  • José M. Ferreira
    • INESC

DOI: 10.1007/BF00134944

Cite this article as:
De Jong, F., Matos, J.S. & Ferreira, J.M. J Electron Test (1991) 2: 77. doi:10.1007/BF00134944


The test technique called “boundary scan test” (BST) offers new opportunities in testing but confronts users with new problems too. The implementation of BST in a chip has become an IEEE standard and users on board level are the next group to begin thinking about using the new possibilities. This article addresses some of the questions about changes in board-level testing and fault diagnosis. The fault model itself is also affected by using BST. Trivial items are extended with more sophisticated details in order to complete the fault model. Finally, BST appears to be a test technique that offers a high degree of detectability on board level, but for diagnosis, some additional effort has to be made.

Key words

boundary scan testBST-netdiagnosisfault modelingPCB testingtest-pattern generation

Copyright information

© Kluwer Academic Publishers 1991