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Data cache organization for accurate timing analysis

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Abstract

Caches are essential to bridge the gap between the high latency main memory and the fast processor pipeline. Standard processor architectures implement two first-level caches to avoid a structural hazard in the pipeline: an instruction cache and a data cache. For tight worst-case execution times it is important to classify memory accesses as either cache hit or cache miss. The addresses of instruction fetches are known statically and static cache hit/miss classification is possible for the instruction cache. The access to data that is cached in the data cache is harder to predict statically. Several different data areas, such as stack, global data, and heap allocated data, share the same cache. Some addresses are known statically, other addresses are only known at runtime. With a standard cache organization all those different data areas must be considered by worst-case execution time analysis. In this paper we propose to split the data cache for the different data areas. Data cache analysis can be performed individually for the different areas. Access to an unknown address in the heap does not destroy the abstract cache state for other data areas. Furthermore, we propose to use a small, highly associative cache for the heap area. We designed and implemented a static analysis for this cache, and integrated it into a worst-case execution time analysis tool.

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Acknowledgements

We would like to thank the anonymous reviewers for their detailed comments, which helped to improve the paper. This research has received partial funding from the European Community’s Seventh Framework Programme [FP7/2007-2013] under grant agreement number 216682 (JEOPARD).

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Authors and Affiliations

  1. Department of Informatics and Mathematical Modeling, Technical University of Denmark, 2800, Kgs. Lyngby, Denmark

    Martin Schoeberl

  2. Institute of Computer Engineering, Vienna University of Technology, Vienna, Austria

    Benedikt Huber & Wolfgang Puffitsch

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  1. Martin Schoeberl
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Correspondence to Martin Schoeberl.

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Schoeberl, M., Huber, B. & Puffitsch, W. Data cache organization for accurate timing analysis. Real-Time Syst 49, 1–28 (2013). https://doi.org/10.1007/s11241-012-9159-8

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