We present a Quality of Service (QoS)-supported on-chip communication that increases the shared communication resources for multi-processor systems on chip. Time-critical embedded systems require tight guaranteed services in terms of throughput, latency etc. in order to comply to hard real-time constraints. Typically, guaranteed-service schemes require dedicated/reserved resources (i.e. links) for communication and thus suffer from low resource utilization. So improving the bandwidth utilization by using the unused bandwidth among the other competing transactions in a fair fashion is an important issue. To the best of our knowledge, we are presenting the first approach for on-chip communication that provides a high resource utilization under a transaction-specific, flexible communication scheme. It provides tight time-related guarantees through our bounded arbitration scheme considering the lower and the upper bounds for each type of transactions. We demonstrate its advantages by means of a complete MPEG4 video decoder case study analysis and achieve under certain constraints a bandwidth utilization of up to 100% and 97% on average with a guaranteed 100% bandwidth. Thus, we provide an on-chip communication scheme that provides high bandwidth utilization while providing tight guarantee.
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R. Ho, K. Mai and M. Horowitz, The Future of Wires, Proceedings of the IEEE, Vol. 89, pp. 490–504 (April 2001).
W. Dally and B. Towles, Route Packets, Not Wires: On-chip Interconnection Networks, Proceedings of the Design, Automation Conf. (DAC’01), pp. 684–689, (June 2001).
P. Guerrier and A. Greiner, A Generic Architecture for On-Chip Packet Switched Interconnections, Proceedings of the Design, Automation and Test in Europe conf. (DATE), pp. 250–256 (March 2000).
P. Wielage and K. Goossens, Networks on Silicon: Blessing or Nightmare?, Proceedings of the Euromicro Symposium on Digital Systems Design (DSD), pp. 196 (2002).
U. Y. Ogras, J. Hu, and R. Marculescu, Key Research Problems in NoC Design: A Holistic Perspective, Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign And System Synthesis, pp. 69–74 (September 2005).
A. Jantsch and H. Tenhunen (Eds), Networks-on-Chip, Kluwer (2003).
J. Henkel, W. Wolf, and S. Chakradhar, On-Chip Networks: A Scalable Communication-Centric Embedded System Design Paradigm, Int. Conf. VLSI Design, pp. 845 (2004).
E. Rijpkema, K. Goossens, A. Radulescu, J. Dielissen, J. van Meerbergen, P. Wielage, and E. Waterlander, Trade-offs in the Design of a Router with both Guaranteed and Best-effort Services for Networks on-Chip, Proceedings of the Design, Automation and Test in Europe Conf. (DATE) (March 2003).
M. Dall’Osso, G. Biccari, L. Giovannini, D. Bertozzi, and L. Benini, Xpipes: A Latency Insensitive Parameterized Network-on-Chip Architecture for Multi- Processor SoCs, ICCD, pp. 536–539 (2003).
I. Saastamoinen, D.Siguenza-Tortosa, and J. Nurmi, Interconnect IP Node For Future System-on-Chip Designs, Proceedings of The First IEEE International Workshop on Electronic Design, Test and Applications, pp. 116–120 (January 2002).
Benini L., De Micheli G. (2002). Networks on Chips: A New SoC Paradigm. Proceedings of IEEE Computer 35(1): 70–78
Goossens K., Dielissen J., Radulescu A. (Sept-Oct 2005). Æthereal Network on Chip: Concepts, Architectures, and Implementations. IEEE Design and Test of Computers 22: 414–421
E. Bolotin, I. Cidon, R. Ginosar, and A. Kolodny, QNoC: QoS Architecture and Design Process for Network on Chip, Special issue on Networks on Chip, The Journal of Systems Architecture, 105–128 (December 2003).
Harmanci M.D., Escudero N.P., Leblebici Y., Ienne P. (2005). Quantitative Modelling and Comparison of Communication Schemes to Guarantee Quality-of-Service in Networks-on-Chip. International Symposium on Low Power Electronics and Design. 2: 1782–1785
M. D. Harmanci, N. P. Escudero, Y. Leblebici, and P. Ienne, Providing QoS to Connection-less Packet-switched NoC by Implementing DiffServ Functionalities, International Symposium on System-on-Chip, pp. 37–40 (2004).
N. Kavaldjiev, Gerard J. M. Smit, and Pierre G. Jansen, A Virtual Channel Router for On-chip Networks, Proceedings of the IEEE International SOC Conference, pp. 289–293 (September 2004).
N. Kavaldjiev, Gerard J. M. Smit, Pierre G. Jansen, and Pascal T. Wolkotte, A Virtual Channel Network-on-Chip for GT and BE Traffic, Proceedings of the International Symposium on VLSI (ISVLSI’06), pp. 211–216 (March 2006).
M. A. Al Faruque, G. Weiss, and J. Henkel, Bounded Arbitration Algorithm for QoS-Supported On-Chip Communication, Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/software Codesign and System Synthesis, pp. 76–81 (October 2006).
http://www.xvid.org/.
J. Duato, L. Ni, and S. Yalamanchili, Interconnection Networks: An Engineering Approach, Morgan Kaufmann Publishers (2002).
L. M. Ni and P. K. McKinley, A Survey of Wormhole Routing Techniques in Direct Networks, IEEE Computer, 62–75, (February 1993).
OCP, International Partnership. http://www.ocpip.org/ (August 2006).
http://www.prodesigncad.com.
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Large parts of this work have previously been published at the IEEE International Conference on Hardware/Software Codesign and System Synthesis (Codes+ISSS), 2006.
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Faruque, M.A.A., Henkel, J. QoS-supported On-chip Communication for Multi-processors. Int J Parallel Prog 36, 114–139 (2008). https://doi.org/10.1007/s10766-007-0039-0
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DOI: https://doi.org/10.1007/s10766-007-0039-0