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Architecture and applications for an All-FPGA parallel computer

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Abstract

The Reconfigurable Computing Cluster (RCC) project has been investigating unconventional architectures for high end computing using a cluster of FPGA devices connected by a high-speed, custom network. Most applications use the FPGAs to realize an embedded System-on-a-Chip (SoC) design augmented with application-specific accelerators to form a message-passing parallel computer. Other applications take a single accelerator core and tessellate the core across all of the devices, treating them like a large virtual FPGA. The experimental hardware has also been used for basic computer research by emulating novel architectures. This article discusses the genesis of the over-arching project, summarizes results of individual investigations that have been completed, and how this approach may prove useful in the investigation of future Exascale systems.

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Acknowledgements

The authors would like to thank our friends and colleagues—William V. Kritikos, Andrew G. Schmidt, Shan Yuan Gao, Ashwin A. Mendon, and Bin Huang—who advanced many of the projects summarized in this report.

This project was supported in part by the National Science Foundation under NSF Grants CNS 05-51688 (CRI) and CNS 04-10790 (EHS). The opinions expressed are those of the authors and not necessarily those of the Foundation.

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  1. Reconfigurable Computing Systems Laboratory, University of North Carolina at Charlotte, 9201 University City Blvd, Charlotte, NC, 28223, USA

    Yamuna Rajasekhar & Ron Sass

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  1. Yamuna Rajasekhar
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  2. Ron Sass
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Correspondence to Yamuna Rajasekhar.

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Rajasekhar, Y., Sass, R. Architecture and applications for an All-FPGA parallel computer. Cluster Comput 17, 315–325 (2014). https://doi.org/10.1007/s10586-013-0278-3

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