Abstract
Unconditional stability of the high-gain amplifiers is a mandatory requirement for a reliable steady-state condition of time-discrete systems, especially for all blocks designed to sample-and-hold (S/H) circuits. Compared to differential path, the common-mode feedback loop is often affected by poles and zeros shifting that degrades the large signal response of the amplifiers. This drawback is made worse in some well-known topologies as the difference-differential amplifier (DDA) that shows non-constant transconductance and poor linearity. This work proposes a body-driven positive-feedback frequency compensation technique (BD-PFFC) to improve the linearity for precision DDA-based S/H applications. Theoretical calculations and circuit simulations carried out in a 0.13 μm process are also given to demonstrate its validity.
Similar content being viewed by others
References
Schetzen, M. (2006). The Volterra and Wiener theories of nonlinear systems. New York: Krieger Publishing Company.
Brown, T. W., Hakkarainen, M., & Fiez, T. S. (2009). Frequency-dependent sampling linearity. IEEE Transactions on Circuits and Systems I: Regular Papers, 56(4), 740–753.
Sivashankar, N., & Khargonekar, P. P. (1991). Robust stability and performance analysis of sampled-data systems. In IEEE Conference on Decision and Control (pp. 881–886), IEEE Conf. Pub., doi:10.1109/CDC.1991.261446.
Pude, M., Mukund, P. R., Singh, P., & Burleson, J. (2008). Using positive feedback to overcome gmro limitations in scaled CMOS amplifier design. In Midwest Symposium on Circuits and Systems (pp. 807–810), IEEE Conf. Pub., doi:10.1109/MWSCAS.2008.4616922.
Schlarmann, M. E., Malik, S. Q., & Geiger, R. L. (2002). Positive feedback gain-enhancement techniques for amplifier design. In IEEE International Symposium on Circuits and Systems (pp. 37–40), IEEE Conf. Pub., doi:10.1109/ISCAS.2002.1010917.
Annema, A. J., Nauta, B., Van Langevelde, R., & Tuinhout, H. (2005). Analog circuits in ultra-deep-submicron CMOS. IEEE Journal of Solid State Circuits, 40(1), 132–143.
Carrillo, J. M., Torelli, G., Perez-Aloe, R., & Duque-Carrillo, J. F. (2007). 1–V Rail-to-rail CMOS OpAmp with improved bulk-driven input stage. IEEE Journal of Solid-State Circuits, 42(3), 508–517.
Semiconductor Industry Association. (2010). International technology roadmap for semiconductors. Available at: http://www.itrs.net/. Accessed 20 July 2011.
Centurelli, F., Simonetti, A., & Trifiletti, A. (2009). Near-optimum switched capacitor sample-and-hold circuit. In IEEE NORCHIP (pp. 1–4), IEEE Conf. Pub., doi:10.1109/NORCHP.2009.5397857.
Centurelli, F., Simonetti, A., & Trifiletti, A. (2008). Switched capacitor sample-and-hold circuit with input signal range beyond supply voltage. In IEEE NORCHIP (pp. 75–78), IEEE Conf. Pub., doi:10.1109/NORCHP.2008.4738286.
Centurelli, F., Simonetti, A., & Trifiletti, A. (2007). A sample-and-hold circuit with very low gain error for time interleaving applications. In European Conference on Circuit Theory and Design (pp. 456–459), IEEE Conf. Pub., doi:10.1109/ECCTD.2007.4529631.
Sackinger, E., & Guggenbuhl, W. (1987). A versatile building block: The CMOS differential difference amplifier. IEEE Journal of Solid-State Circuits, 22(2), 287–294.
Duque-Carrillo, J., Torelli, G., Perez-Aloe, R., Valverde, J., & Maloberti, F. (1995). Fully differential basic bulding blocks based on fully differential difference amplifiers with unity-gain difference feedback. IEEE Transaction on Circuits and Systems-I, 42(3), 190–192.
Shrivastava, M., Mehta, R., Gupta, S., Agrawal, N., Baghini, M. S., Sharma, D. K., et al. (2011). Toward system on chip (SoC) development using FinFET technology: Challenges, solutions, process co-development & optimization guidelines. IEEE Transactions on Electron Devices, 58(6), 1597–1607.
Miguel, J. M. A., Lopez-Martin, A. J., Acosta, L., Ramirez-Angulo, J., & Carvajal, R. G. (2011). Using floating gate and quasi-floating gate techniques for rail-to-rail tunable CMOS transconductor design. IEEE Transactions on Circuits and Systems I: Regular Papers, 58(7), 1604–1614.
Fried, R., & Enz, C. C. (1996). Bulk driven MOST transconductor with extended linear range. Electronics Letters, 32(7), 638–640.
Blalock, B. J., Li, H. W., Allen, P. E., & Jackson, S. A. (2000). Body-driving as a low-voltage analog design technique for CMOS technology. In Southwest Symposium on Mixed-Signal Design (pp. 113–118), IEEE Conf. Pub., doi:10.1109/SSMSD.2000.836457.
Von Arnim, K., Borinski, E., Seegebrecht, P., Fiedler, H., Brederlow, R., Thewes, R., et al. (2005). Efficiency of body biasing in 90-nm CMOS for low-power digital circuits. IEEE Journal of Solid-State Circuits, 40(7), 1549–1556.
Inchang, S., & Fox, R. M. (2004). Comparison of quasi-/pseudo-floating gate techniques. In IEEE International Symposium on Circuits and Systems (pp. 365–368), IEEE Conf. Pub., doi:10.1109/ISCAS.2004.1328207.
Agostinelli, M., Alioto, M., Esseni, D., & Selmi, L. (2010). Leakage–delay tradeoff in FinFET logic circuits: A comparative analysis with bulk technology. IEEE Transactions on VLSI Systems, 18(2), 232–245.
Pingli, H., Szukang, H., Lu, V., Peiyuan, W., Seung-Chul, L., Wenbo, L., et al. (2011). SHA-less pipelined ADC with in situ background clock-skew calibration. IEEE Journal of Solid-State Circuits, 46(8), 1893–1903.
Devarajan, S., Singer, L., Kelly, D., Decker, S., Kamath, A., & Wilkins, P. (2009). A 16b 125MS/s 385mW 78.7 dB SNR CMOS pipeline ADC. In IEEE International Solid-State Circuits Conference Digest of Technical Papers, (pp. 86–87, 87a), IEEE Conf. Pub., doi:10.1109/ISSCC.2009.4977320.
Carrillo, J. M., Torelli, G., Dominguez, M. A., Perez-Aloe, R., Valverde, J. M., & Duque-Carrillo, J. F. (2010). A family of low-voltage bulk-driven CMOS continuous-time CMFB circuits. IEEE Transactions on Circuits and Systems II, 57(11), 863–867.
Castano, F., Torelli, G., Perez-Aloe, R., & Carrillo, J. M. (2010). Low-voltage rail-to-rail bulk-driven CMFB network with improved gain and bandwidth. In IEEE International Conference on Electronics, Circuits, and Systems (pp. 207–210), IEEE Conf. Pub., doi:10.1109/ICECS.2010.5724490.
Gasulla, M., Casas, O., & Pallas-Areny, R. (2000). On the common mode response of fully differential circuits. In IEEE Instrumentation and Measurement Technology Conference (pp. 1045–1049), IEEE Conf. Pub., doi:10.1109/IMTC.2000.848900.
Giustolisi, G., Palmisano, G., & Palumbo, G. (2000). CMRR frequency response of CMOS operational transconductance amplifiers. IEEE Transactions on Instrumentation and Measurement, 49(1), 137–143.
Hernandez-Garduno, D., & Silva-Martinez, J. (2005). Continuous-time common-mode feedback for high-speed switched-capacitor networks. IEEE Journal of Solid-State Circuits, 40(8), 1610–1617.
Choksi, O., & Carley, L. R. (2003). Analysis of switched-capacitor common-mode feedback circuit. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 50(12), 906–917.
Banu, M., Khoury, J. M., & Tsividis, Y. (1988). Fully differential operational amplifiers with accurate output balancing. IEEE Journal of Solid-State Circuits, 23(6), 1410–1414.
Weixun, Y., & Zimmermann, H. (2008). Continuous-time common-mode feedback circuit for applications with large output swing and high output impedance. In Workshop on Design and Diagnostics of Electronic Circuits and Systems (pp. 1–5), IEEE Conf. Pub., doi:10.1109/DDECS.2008.4538757.
Gupta, A. K., Dhanasekaran, V., Soundarapandian, K., & Sanchez-Sinencio, E. (2006). Multipath common-mode feedback scheme suitable for high-frequency two-stage amplifiers. IEE Electronics Letters, 42(9), 499–500.
Babanezhad, J. N. (1998). A rail-to-rail CMOS Opamp. IEEE Journal of Solid-State Circuits, 23(6), 1414–1417.
Sooch, N. S. (1985). MOS cascode current mirror. U.S. patent 4,550,284.
Monticelli, D. M. (1986). A quad CMOS single-supply Opamp with rail-to-rail output swing. IEEE Journal of Solid-State Circuits, 21,1026–1034.
Johns, D., Martin, K. (1996). Analog integrated circuit design. New York: Wiley. ISBN-13: 978-0471144489.
Jacob Baker, R. (2010). CMOS circuit design, layout, and simulation (3rd ed.), IEEE Press Series on Microelectronic Systems. New York: Wiley-IEEE Press. ISBN 13: 978-0470881323.
Hung, C.-C., Ismail, M., Halonen, K., & Porra, V. (1997). Low-voltage rail-to-rail CMOS differential difference amplifier. In IEEE International Symposium on Circuits and Systems (pp. 145–148), IEEE Conf. Pub., doi:10.1109/ISCAS.1997.608637.
Srivastava, A., & Govindarajan, D. (2002). A fast ALU design in CMOS for low voltage operation. Journal VLSI Design, 14(4), 315–327.
Centurelli, F., Simonetti, A., & Trifiletti, A. (2008). A low-power sample-and-hold circuit based on a switched-opamp technique. In International Conference on Signals and Electronic Systems (ICSES’08) (pp. 105–108), IEEE Conf. Pub., doi:10.1109/ICSES.2008.4673369.
Recoules, H., Bouchakour, R., & Loumeau, R. (1998). A comparative study of two SC-CMFB networks used in fully differential OTA. In IEEE International Conference on Electronics, Circuits and Systems (pp. 291–294), IEEE Conf. Pub., doi:10.1109/ICECS.1998.814883.
Author information
Authors and Affiliations
Corresponding author
Rights and permissions
About this article
Cite this article
Centurelli, F., Simonetti, A. & Trifiletti, A. An improved common-mode feedback loop for the differential-difference amplifier. Analog Integr Circ Sig Process 74, 33–48 (2013). https://doi.org/10.1007/s10470-012-9961-1
Received:
Revised:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s10470-012-9961-1