Abstract
Software defined radios (SDR) wideband mobile terminals must be capable of data processing while consuming low power and keeping the design and manufacturing costs as low as possible. SDR can combine high performance signal processing and flexibility, but power efficiency of SDR nodes is an issue that needs to be addressed. Analysis of power consumption for various target technologies is challenging, since each technology typically contains its own benchmarking tools and thus, results are not comparable. In this paper, we illustrate how the GroundHog2009 benchmark suite, designed to be platform independent, can be used to evaluate power dissipation of four modern FPGAs and one microcontroller. We also introduce a generic RTL library for the GroundHog2009 design cases and test bench infra-structure to make the toolset usage easy. In addition, we show that power can be saved by using clock management, available on one of the FGPA-boards. The power savings range from 38 to 1,150 %.
Similar content being viewed by others
References
Abidi, A. (2007). The path to the software-defined radio receiver. IEEE Journal of Solid-State Circuits, 42(5), 954–966.
Akabane, K., Shiba, H., Matsui, M., Umehira, M., Uehara, K.(2005). Performance evaluation of reconfigurable processor for SDR mobile terminals and SDR base station using autonomous adaptive control technology. ICICS (pp. 148–152).
Jamieson, P., Becker, T., Luk, W., Cheung, P. Y. K., Rissa, T., Pitkänen, T. (2009). Benchmarking reconfigurable architectures in the mobile domain. Proceedings of IEEE Symposium on Field-Programmable Custom Computing Machines (pp. 131–138).
Yang, S. (1991). Logic synthesis and optimization benchmarks user guide. (Version 3.0).
Poon, K., Yan, A., Wilton, S. (2002). A flexible power model for FPGAs. Proceedings of International Conference on Field Programmable Logic and Applications, (pp. 312–321).
Anderson, J., & Najm, F. (2004). Power estimation techniques for FPGAs. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 12(10), 1015–1027.
Tinmaung, K. O., Howland, D., Tessier, R. (2007). Power-aware FPGA logic synthesis using binary decision diagrams. FPGA, 148–155.
OpenCore, project GroundHog2009. (2010). Accessed March 10, 2012, from http://opencores.org/project,groundhog2009_repository,downloads.
Jamieson, P., Becker, T., Cheung, P. Y. K., Luk, W., Rissa, T., Pitkänen, T. (2010). Benchmarking and evaluating reconfigurable architectures in the mobile domain. ACM Transactions on Design Automation of Electronic Systems. doi:10.1145/1698759.1698764.
Becker T., Jamieson, P., Luk, W., Cheung, P. Y. K., Rissa, T. (2010). Power characterization for fine-grain reconfigurable fabrics. International Journal of Reconfigurable Computing. doi:10.1155/2010/787405.
Advanced Encryption Standard (AES). (2001). Federal information processing standards publication 197, November, 2001.
Welch, T. A. (1984). A technique for high-performance data compression. IEEE Computer, 17(6), 8–19.
Altera DE2. (2006). Development and education board user manual.
SiliconBlue. iCE DiCE. (2009): iCE65L04 ultra low-power FPGA known good die.
Actel. (2008). Igloo handbook.
Lattice. (2011). Mach XO2: The do-it-All PLD for low density applications.
Cypress. (2011). PSoC 3: CY8C38 family data sheet.
National Instruments. (2010). PXI-1033 Chassis, Data sheet.
National Instruments. (2010) PXI-4130 Power SMU, Data sheet.
National Instruments, TB-2709 Sampling DAQ, Data sheet (2010).
Author information
Authors and Affiliations
Corresponding author
Rights and permissions
About this article
Cite this article
Pitkänen, T., Jamieson, P., Becker, T. et al. Power consumption benchmarking for reconfigurable platforms. Analog Integr Circ Sig Process 73, 649–659 (2012). https://doi.org/10.1007/s10470-012-9950-4
Received:
Revised:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s10470-012-9950-4