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Analog circuit synthesis performing fast Pareto frontier exploration and analysis through 3D graphs

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Abstract

This paper presents a technique for performing analog design synthesis at circuit level providing feedback to the designer through the exploration of the Pareto frontier. A modified simulated annealing which is able to perform crossover with past anchor points when a local minimum is found which is used as the optimization algorithm on the initial synthesis procedure. After all specifications are met, the algorithm searches for the extreme points of the Pareto frontier in order to obtain a non-exhaustive exploration of the Pareto front. Finally, multi-objective particle swarm optimization is used to spread the results and to find a more accurate frontier. Piecewise linear functions are used as single-objective cost functions to produce a smooth and equal convergence of all measurements to the desired specifications during the composition of the aggregate objective function. To verify the presented technique two circuits were designed, which are: a Miller amplifier with 96 dB Voltage gain, 15.48 MHz unity gain frequency, slew rate of 19.2 V/μs with a current supply of 385.15 μA, and a complementary folded cascode with 104.25 dB Voltage gain, 18.15 MHz of unity gain frequency and a slew rate of 13.370 MV/μs. These circuits were synthesized using a 0.35 μm technology. The results show that the method provides a fast approach for good solutions using the modified SA and further good Pareto front exploration through its connection to the particle swarm optimization algorithm.

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Authors and Affiliations

  1. Integrated Systems Laboratory LSI, Electronic Systems Engineering Department, Polytechnic School, University of São Paulo, Av. Prof. Luciano Gualberto, 158. Trav.3., São Paulo, SP, Brazil

    Tiago Oliveira Weber & Wilhelmus A. M. Van Noije

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  1. Tiago Oliveira Weber
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  2. Wilhelmus A. M. Van Noije
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Correspondence to Tiago Oliveira Weber.

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Weber, T.O., Van Noije, W.A.M. Analog circuit synthesis performing fast Pareto frontier exploration and analysis through 3D graphs. Analog Integr Circ Sig Process 73, 861–871 (2012). https://doi.org/10.1007/s10470-012-9939-z

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  • DOI: https://doi.org/10.1007/s10470-012-9939-z

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