Abstract
Bang-bang phase detector based PLLs are simple to design, suffer no systematic phase error, and can run at the highest speed a process can make a working flip-flop. For these reasons designers are employing them in the design of very high speed Clock Data Recovery (CDR) architectures. The major drawback of this class of PLL is the inherent jitter due to quantized phase and frequency corrections. Reducing loop gain can proportionally improve jitter performance, but also reduces locking time and pull-in range. This paper presents a novel PLL design that dynamically scales its gain in order to achieve fast lock times while improving jitter performance in lock. Under certain circumstances the design also demonstrates improved capture range. This paper also analyses the behaviour of a bang-bang type PLL when far from lock, and demonstrates that the pull-in range is proportional to the square root of the PLL loop gain.
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Michael Chan received his bachelor degrees in Electrical Engineering and Computer Science from the University of Queensland in 2003. He is currently working towards his PhD at the same institution. His research interests include the design of high-speed clock and data recovery systems, and high speed phase locked loops.
Adam Postula received the M.S. degree in electrical engineering from the Warsaw University of Technology, Poland, in 1974 and the Ph.D. degree in signal processing from the Poznan University of Technology, Poland, in 1981. He was an Electronic System Designer with ABB Sweden and a Researcher with the Royal Institute of Technology, Stockholm, Sweden, from 1983 to 1992. He led the development of high-level synthesis tools at the Swedish Institute of Microelectronics and was engaged in VHDL standardization in Europe. Since 1995, he has been a Senior Lecturer in the Department of Computer Science and Electrical Engineering, University of Queensland, Brisbane, Australia. His research interests include digital system design methodology, synthesis of digital systems, specialized processor architectures, and VLSI signal processing.
Ding Yong received his PhD from University of London in electrical engineering in 1991. He was with National University of Singapore as a research scientist working in industrial research projects on data channel and servo-system for CD technology. In 1995, he joined VLSI design group of Western Digital as a principle engineer, where he was engaged in the IC design of Hard Disk Controller and CD-ROM Decoder and Controller. From 2000, he has been leading a mixed-signal design group as design manager and chief architect with Nano Silicon responsible for development of high-speed serial data transmission IPs.
Lech Jóźwiak is an Associate Professor, Head of the Section of Digital Circuits and Formal Methods, at the Faculty of Electrical Engineering, Eindhoven University of Technology, The Netherlands. He received his M.Sc. and Ph.D. degrees in Electronics from the Warsaw University of Technology, Warsaw, Poland, in 1976 and 1982, respectively. From 1979 to 1986, he was a chief of two R&D teams in the Research Institute of Computers in Warsaw, and consultant to the United Nations Industrial Development Organization and industry. From 1986, he works mainly in the Netherlands, but also from time to time in USA, Canada, Australia, Belgium and Poland, combining advanced theoretical research with professional engineering practice and collaborating with industry, academia and governments. He is an author of a new information-driven approach to digital circuit synthesis, and new theories and methodologies of information relationships and measures, general decomposition and quality-driven design that have a considerable practical importance. He is also a creator of a number of practical products in the fields of application-specific (embedded) systems and EDA tools. His research interests include system, circuit, information and design theories and technologies, decision and optimization methodology, artificial intelligence, circuit and system design and EDA, re-configurable and massively parallel high-performance systems, embedded systems, and system dependability, analysis and validation. He is an author of more than 130 journal and conference papers and of some book chapters. He is a Director of EUROMICRO, co-founder and Steering Committee Chair of the EUROMICRO Symposium on Digital System Design, VIP in the IEEE International Symposium on Quality Electronic Design, program committee member of many other conferences, member of IEEE, EDAA, and of the Advisory Committee of the IEE Professional Network Embedded and Real-Time System Engineering. He is an advisor to the industry, Ministry of Economy and Commission of the European Communities in the fields of microelectronics, information technology, technology development and transfer, and SMEs.
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Chan, M.J., Postula, A., Ding, Y. et al. A bang-bang PLL employing dynamic gain control for low jitter and fast lock times. Analog Integr Circ Sig Process 49, 131–140 (2006). https://doi.org/10.1007/s10470-006-7581-3
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DOI: https://doi.org/10.1007/s10470-006-7581-3