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Design techniques for fault-tolerant systolic arrays

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Abstract

A systematic approach of designing fault-tolerant systolic architectures is proposed in this paper. In this approach, redundant computations are introduced at the algorithmic level by deriving three versions of a given algorithm. Fault-tolerant systolic array is constructed by merging the corresponding systolic array of the three versions of the algorithm. The merging method attempts to obtain the fault-tolerant systolic array at minimal cost in terms of area and speed. It is based on rescheduling input data, rearranging data flow, and increasing the utilization of the array cells. The resulting design can detect and tolerate all single permanent and temporary faults and the majority of the multiple fault patterns with high probability.

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Authors and Affiliations

  1. Department of Electrical and Computer Engineering, Concordia University, 1455 De Maisonneuve Blvd. West, H3G 1M8, Montreal, Quebec, Canada

    M. O. Esonu & A. J. Al-Khalili

  2. Electrical and Computer Engineering Department, Syracuse University, 113 Link, 13244, Syracuse, N. Y., USA

    S. Hariri

  3. ECE Dept., Royal Military College, K7K 5L0, Kingston, Ontario, Canada

    D. Al-Khalili

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  1. M. O. Esonu
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  2. A. J. Al-Khalili
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  3. S. Hariri
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  4. D. Al-Khalili
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Esonu, M.O., Al-Khalili, A.J., Hariri, S. et al. Design techniques for fault-tolerant systolic arrays. Journal of VLSI Signal Processing 11, 151–168 (1995). https://doi.org/10.1007/BF02106828

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  • DOI: https://doi.org/10.1007/BF02106828

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