Computer-Aided Verification

1. Front Matter

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2. Temporal logic model checking: Two techniques for avoiding the state explosion problem

   • Edmund M. Clarke Jr.

   Pages 1-1

3. Automatic verification of extensions of hardware descriptions

   • Hans Eveking

   Pages 2-12

4. Papetri : Environment for the analysis of PETRI nets

   • G. Berthelot, C. Johnen, L. Petrucci

   Pages 13-22

5. Verifying temporal properties of sequential machines without building their state diagrams

   • Olivier Coudert, Jean Christophe Madre, Christian Berthet

   Pages 23-32

6. Formal verification of digital circuits using symbolic ternary system models

   • Randal E. Bryant, Carl-Johan H. Seger

   Pages 33-43

7. Vectorized model checking for computation tree logic

   • Hiromi Hiraishi, Shintaro Meki, Kiyoharu Hamaguchi

   Pages 44-53

8. Introduction to a computational theory and implementation of sequential hardware equivalence

   • Carl Pixley

   Pages 54-64

9. Auto/autograph

   • Valérie Roy, Robert de Simone

   Pages 65-75

10. A data path verifier for register transfer level using temporal logic language Tokio

    • Hiroshi Nakamura, Yuji Kukimoto, Masahiro Fujita, Hidehiko Tanaka

    Pages 76-85

11. The use of model checking in ATPG for sequential circuits

    • P. Camurati, M. Gilli, P. Prinetto, M. Sonza Reorda

    Pages 86-95

12. Compositional design and verification of communication protocols, using labelled petri nets

    • Jean Christopeh Lloret, Pierre Azéma, François Vernadat

    Pages 96-105

13. Issues arising in the analysis of L.0

    • Linda Ness

    Pages 106-115

14. Automated RTL verification based on predicate calculus

    • M. Langevin

    Pages 116-125

15. On using protean to verify ISO FTAM protocol

    • R. Lai, K. R. Parker, T. S. Dillon

    Pages 126-135

16. Quantitative temporal reasoning

    • E. Allen Emerson, A. K. Mok, A. P. Sistla, Jai Srinivasan

    Pages 136-145

17. Using partial-order semantics to avoid the state explosion problem in asynchronous systems

    • David K. Probst, Hon F. Li

    Pages 146-155

18. A stubborn attack on state explosion

    • Antti Valmari

    Pages 156-165

19. Using optimal simulations to reduce reachability graphs

    • Ryszard Janicki, Maciej Koutny

    Pages 166-175

20. Using partial orders to improve automatic verification methods

    • Patrice Godefroid

    Pages 176-185

This volume contains the proceedings of the second workshop on Computer Aided Verification, held at DIMACS, Rutgers University, June 18-21, 1990. Itfeatures theoretical results that lead to new or more powerful verification methods. Among these are advances in the use of binary decision diagrams, dense time, reductions based upon partial order representations and proof-checking in controller verification. The motivation for holding a workshop on computer aided verification was to bring together work on effective algorithms or methodologies for formal verification - as distinguished, say,from attributes of logics or formal languages. The considerable interest generated by the first workshop, held in Grenoble, June 1989 (see LNCS 407), prompted this second meeting. The general focus of this volume is on the problem of making formal verification feasible for various models of computation. Specific emphasis is on models associated with distributed programs, protocols, and digital circuits. The general test of algorithm feasibility is to embed it into a verification tool, and exercise that tool on realistic examples: the workshop included sessionsfor the demonstration of new verification tools.

• Algorithms
• Attribut
• Session
• algorithm
• computer
• formal language
• formal languages
• formal verification
• tools
• verification

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