Skip to main content
  • Conference proceedings
  • © 2005

Correct Hardware Design and Verification Methods

13th IFIP WG 10.5Advanced Research, Working Conference, CHARME 2005, Saarbrücken, Germany, October 3-6, 2005, Proceedings

Conference proceedings info: CHARME 2005.

Buy it now

Buying options

eBook USD 39.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book USD 54.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Other ways to access

This is a preview of subscription content, log in via an institution to check for access.

Table of contents (42 papers)

  1. Front Matter

  2. Tutorial

    1. Towards the Pervasive Verification of Automotive Systems

      • Thomas In der Rieden, Dirk Leinenbach, Wolfgang Paul
      Pages 3-4
  3. Functional Approaches to Design Description

    1. Wired: Wire-Aware Circuit Design

      • Emil Axelsson, Koen Claessen, Mary Sheeran
      Pages 5-19
    2. Formalization of the DE2 Language

      • Warren A. Hunt Jr., Erik Reeber
      Pages 20-34
  4. Game Solving Approaches

    1. Finding and Fixing Faults

      • Stefan Staber, Barbara Jobstmann, Roderick Bloem
      Pages 35-49
    2. Verifying Quantitative Properties Using Bound Functions

      • Arindam Chakrabarti, Krishnendu Chatterjee, Thomas A. Henzinger, Orna Kupferman, Rupak Majumdar
      Pages 50-64
  5. Abstraction

    1. How Thorough Is Thorough Enough?

      • Arie Gurfinkel, Marsha Chechik
      Pages 65-80
    2. Interleaved Invariant Checking with Dynamic Abstraction

      • Liang Zhang, Mukul R. Prasad, Michael S. Hsiao
      Pages 81-96
  6. Algorithms and Techniques for Speeding (DD-Based) Verification 1

    1. Efficient Symbolic Simulation via Dynamic Scheduling, Don’t Caring, and Case Splitting

      • Viresh Paruthi, Christian Jacobi, Kai Weber
      Pages 114-128
    2. Achieving Speedups in Distributed Symbolic Reachability Analysis Through Asynchronous Computation

      • Orna Grumberg, Tamir Heyman, Nili Ifergan, Assaf Schuster
      Pages 129-145
  7. Real Time and LTL Model Checking

    1. Real-Time Model Checking Is Really Simple

      • Leslie Lamport
      Pages 162-175
    2. Temporal Modalities for Concisely Capturing Timing Diagrams

      • Hana Chockler, Kathi Fisler
      Pages 176-190
    3. Regular Vacuity

      • Doron Bustan, Alon Flaisher, Orna Grumberg, Orna Kupferman, Moshe Y. Vardi
      Pages 191-206
  8. Algorithms and Techniques for Speeding Verification 2

    1. Automatic Generation of Hints for Symbolic Traversal

      • David Ward, Fabio Somenzi
      Pages 207-221
    2. A New SAT-Based Algorithm for Symbolic Trajectory Evaluation

      • Jan-Willem Roorda, Koen Claessen
      Pages 238-253

Other Volumes

  1. Correct Hardware Design and Verification Methods

Editors and Affiliations

  • TIMA Laboratory, VDS Group, Grenoble, France

    Dominique Borrione

  • Computer Science Dept., Saarland University, Saarbrücken, Germany

    Wolfgang Paul

Bibliographic Information

Buy it now

Buying options

eBook USD 39.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book USD 54.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Other ways to access