Using Artificial Neural Networks for Analog Integrated Circuit Design Automation

1. Front Matter

   Pages i-xviii

   PDF

2. Introduction

   • João P. S. Rosa, Daniel J. D. Guerra, Nuno C. G. Horta, Ricardo M. F. Martins, Nuno C. C. Lourenço

   Pages 1-8

3. Related Work

   • João P. S. Rosa, Daniel J. D. Guerra, Nuno C. G. Horta, Ricardo M. F. Martins, Nuno C. C. Lourenço

   Pages 9-20

4. Overview of Artificial Neural Networks

   • João P. S. Rosa, Daniel J. D. Guerra, Nuno C. G. Horta, Ricardo M. F. Martins, Nuno C. C. Lourenço

   Pages 21-44

5. Using ANNs to Size Analog Integrated Circuits

   • João P. S. Rosa, Daniel J. D. Guerra, Nuno C. G. Horta, Ricardo M. F. Martins, Nuno C. C. Lourenço

   Pages 45-66

6. ANNs as an Alternative for Automatic Analog IC Placement

   • João P. S. Rosa, Daniel J. D. Guerra, Nuno C. G. Horta, Ricardo M. F. Martins, Nuno C. C. Lourenço

   Pages 67-101

This book addresses the automatic sizing and layout of analog  integrated circuits (ICs) using deep learning (DL) and artificial neural networks (ANN). It explores an innovative approach to automatic circuit sizing where ANNs learn patterns from previously optimized design solutions. In opposition to classical optimization-based sizing strategies, where computational intelligence techniques are used to iterate over the map from devices’ sizes to circuits’ performances provided by design equations or circuit simulations, ANNs are shown to be capable of solving analog IC sizing as a direct map from specifications to the devices’ sizes. Two separate ANN architectures are proposed: a Regression-only model and a Classification and Regression model. The goal of the Regression-only model is to learn design patterns from the studied circuits, using circuit’s performances as input features and devices’ sizes as target outputs. This model can size a circuit given its specifications for a single topology. The Classification and Regression model has the same capabilities of the previous model, but it can also select the most appropriate circuit topology and its respective sizing given the target specification. The proposed methodology was implemented and tested on two analog circuit topologies. 

• Analog IC sizing
• Artificial Neural Networks
• Analog IC Placement
• Electronic Design Automation
• Applied Deep Learning
• Analog IC Design Automation

• Instituto de Telecomunicações, Instituto Superior Técnico, University of Lisbon, Lisbon, Portugal

  João P. S. Rosa, Daniel J. D. Guerra, Nuno C. G. Horta, Ricardo M. F. Martins, Nuno C. C. Lourenço

Nuno Lourenço (M’14) received Licenciado, M.Sc. and Ph.D. degrees in Electrical and Computer Engineering from Instituto Superior Técnico, University of Lisbon, Portugal, in 2005, 2007, and 2014 respectively. He is with Instituto de Telecomunicações in Lisbon since 2005, where he now holds a postdoctoral research position. He is also an invited Assistant Professor in the Department of Electrical and Computer Engineering of IST-UL since 2015. He has authored or co-authored over 50 publications, including patents, books, book chapters, international journals and conferences papers. His research interests include analog and mixed-signal IC design, electronic design automation tools, applied computational intelligence, and deep learning.


Ricardo Martins received the B.Sc., M.Sc. and Ph.D. degrees in Electrical and Computer Engineering from Instituto Superior Técnico – University of Lisbon (IST-UL), Portugal, in 2011, 2012 and 2015, respectively. He iswith Instituto de Telecomunicações since 2011 developing tools for electronic design automation, where he now holds a postdoctoral research position. He is also an invited Assistant Professor in the Department of Electrical and Computer Engineering of IST-UL. He has authored or co-authored about 50 publications, including books, book chapters, international journals and conferences papers. His current research interests include: electronic design automation tools for analog, mixed-signal and radio-frequency integrated circuits, deep nanometer integration technologies, soft computing, machine learning and deep learning.

Nuno Horta (S’89–M’97–SM’11) received the Licenciado, MSc, PhD and Habilitation degrees in Electrical and Computer Engineer from Instituto Superior Técnico (IST), University of Lisbon, Portugal, in 1989, 1992, 1997 and 2014, respectively. In March 1998, he joined the IST Electrical and Computer Engineering Department where he is currently an Associate Professor with Habilitation. Since 1998, he is, also, with Instituto de Telecomunicações, where he is the head of the Integrated Circuits Group. He has supervised more than 100 post-graduation works between MSc and PhD theses. He has authored or co-authored more than 150 publications as books, book chapters, international journals papers and conferences papers. He has also participated as researcher or coordinator in several National and European R&D projects. He was General Chair of AACD 2014, PRIME 2016 and SMACD 2016 and was member of the organizing and technical program committees of several other conferences, e.g., IEEE ISCAS, IEEE LASCAS, DATE, NGCAS, etc. He is Associated Editor of Integration, The VLSI Journal, from Elsevier, and usually acts as reviewer of several prestigious publications, e.g., IEEE TCAD, IEEE TEC, IEEE TCAS, ESWA, ASC, etc. His research interests are mainly in analog and mixed-signal IC design, analog IC design automation, soft computing and data science.

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