Overview
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Table of contents (25 chapters)
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Front Matter
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Models for VLSI Manufacturing Yield
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Array Processors
Keywords
About this book
Higher circuit densities, increasingly more complex application ohjectives, and advanced packaging technologies have suhstantially increased the need to incorporate defect-tolerance and fault-tolerance in the design of VLSI and WSI systems. The goals of defect-tolerance and fault-tolerance are yield enhancement and improved reliahility. The emphasis on this area has resulted in a new field of interdisciplinary scientific research. I n fact, advanced methods of defect/fault control and tolerance are resulting in enhanced manufacturahility and productivity of integrated circuit chips, VI.SI systems, and wafer scale integrated circuits. In 1987, Dr. W. Moore organized an "International Workshop on Designing for Yield" at Oxford University. Edited papers of that workshop were published in reference [II. The participants in that workshop agreed that meetings of this type should he con tinued. preferahly on a yearly hasis. It was Dr. I. Koren who organized the "IEEE Inter national Workshop on Defect and Fault Tolerance in VLSI Systems" in Springfield Massachusetts the next year. Selected papers from that workshop were puhlished as the first volume of this series [21.
Editors and Affiliations
Bibliographic Information
Book Title: Defect and Fault Tolerance in VLSI Systems
Book Subtitle: Volume 2
Editors: C. H. Stapper, V. K. Jain, G. Saucier
DOI: https://doi.org/10.1007/978-1-4757-9957-6
Publisher: Springer New York, NY
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eBook Packages: Springer Book Archive
Copyright Information: Springer Science+Business Media New York 1990
Hardcover ISBN: 978-0-306-43531-7Published: 31 October 1990
Softcover ISBN: 978-1-4757-9959-0Published: 05 May 2013
eBook ISBN: 978-1-4757-9957-6Published: 29 June 2013
Edition Number: 1
Number of Pages: XIII, 316