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Power Aware Computing

  • Book
  • © 2002

Overview

Editors:
  1. Robert Graybill

    1. The Defense Advanced Research Project Agency, Arlington, USA

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    You can also search for this editor in PubMed   Google Scholar

  2. Rami Melhem

    1. University of Pittsburgh, Pittsburgh, USA

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    You can also search for this editor in PubMed   Google Scholar

  • Covers power optimization and energy management at multiple levels
  • Introduces reader to some of the most recent techniques for managing power
  • Presents recent results from the Power Aware Computing and Communications research initiative
  • Discusses measurement and evaluation at the circuit, architecture and application levels

Part of the book series: Series in Computer Science (SCS)

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Table of contents (17 chapters)

  1. Front Matter

    Pages i-xxiv
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  2. Circuit Level Power Management

    1. Front Matter

      Pages 1-1
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    2. Comparative Analysis of Flip-Flops and Application of Data-Gating in Dynamic Flip-Flops for High Speed, Low Active and Low Leakage Power Dissipation

      • Vamsi Srikantam, Mario Martinez
      Pages 3-17

    3. Low Power Sandwich/Spin Tunneling Memory Device

      • Jim Daughton, Arthur Pohm, Russell Beech
      Pages 19-32

  3. Architecture Level Power Management

    1. Front Matter

      Pages 33-33
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    2. Power-Efficient Issue Queue Design

      • Alper Buyuktosunoglu, David H. Albonesi, Stanley Schuster, David Brooks, Pradip Bose, Peter Cook
      Pages 35-58

    3. Micro-Architecture Design and Control Speculation for Energy Reduction

      • Dirk Grunwald
      Pages 59-78

    4. Energy-Exposed Instruction Sets

      • Krste Asanović, Mark Hampton, Ronny Krashinsky, Emmett Witchel
      Pages 79-98

  4. Operating System Level Power Management

    1. Front Matter

      Pages 99-99
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    2. Dynamic Management of Power Consumption

      • Tajana Simunic
      Pages 101-125

    3. Power Management Points in Power-Aware Real-Time Systems

      • Rami Melhem, Nevine AbouGhazaleh, Hakan Aydin, Daniel Mossé
      Pages 127-152

    4. A Power-Aware API for Embedded and Portable Systems

      • Cristiano Pereira, Rajesh Gupta, Paleologos Spanos, Mani Srivastava
      Pages 153-166

  5. Compiler Level Power Management

    1. Front Matter

      Pages 167-167
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    2. PACT HDL: A Compiler Targeting Asics and Fpgas with Power and Performance Optimizations

      • Alex Jones, Debabrata Bagchi, Sartajit Pal, Prith Banerjee, Alok Choudhary
      Pages 169-190

    3. Compiler Optimizations for Low Power Systems

      • Mahmut Kandemir, N. Vijaykrishnan, Mary Jane Irwin
      Pages 191-210

    4. Power-Performance Trade-Offs in Second Level Memory Used by an ARM-Like RISC Architecture

      • Kiran Puttaswamy, Lakshmi Narasimhan Chakrapani, Kyu-Won Choi, Yuvraj Singh Dhillon, Utku Diril, Pinar Korkmaz et al.
      Pages 211-224

  6. Application Level Power Management

    1. Front Matter

      Pages 225-225
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    2. Application-Level Power Awareness

      • Jeffrey A. Barnett
      Pages 227-242

    3. A Power-Aware, Satellite-Based Parallel Signal Processing Scheme

      • Patrick M. Shriver, Maya B. Gokhale, Scott D. Briles, Dong-In Kang, Michael Cai, Kevin McCabe et al.
      Pages 243-259

    4. The Case for Power Management in Web Servers

      • Pat Bohrer, Elmootazbellah N. Elnozahy, Tom Keller, Michael Kistler, Charles Lefurgy, Chandler McDowell et al.
      Pages 261-289
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Keywords

About this book

With the advent of portable and autonomous computing systems, power con­ sumption has emerged as a focal point in many research projects, commercial systems and DoD platforms. One current research initiative, which drew much attention to this area, is the Power Aware Computing and Communications (PAC/C) program sponsored by DARPA. Many of the chapters in this book include results from work that have been supported by the PACIC program. The performance of computer systems has been tremendously improving while the size and weight of such systems has been constantly shrinking. The capacities of batteries relative to their sizes and weights has been also improv­ ing but at a rate which is much slower than the rate of improvement in computer performance and the rate of shrinking in computer sizes. The relation between the power consumption of a computer system and it performance and size is a complex one which is very much dependent on the specific system and the technology used to build that system. We do not need a complex argument, however, to be convinced that energy and power, which is the rate of energy consumption, are becoming critical components in computer systems in gen­ eral, and portable and autonomous systems, in particular. Most of the early research on power consumption in computer systems ad­ dressed the issue of minimizing power in a given platform, which usually translates into minimizing energy consumption, and thus, longer battery life.

Editors and Affiliations

  • The Defense Advanced Research Project Agency, Arlington, USA

    Robert Graybill

  • University of Pittsburgh, Pittsburgh, USA

    Rami Melhem

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