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Logic Synthesis and Optimization

  • Book
  • © 1993

Overview

Editors:
  1. Tsutomu Sasao

    1. Kyushu Institute of Technology, Iizuka, Japan

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Part of the book series: The Springer International Series in Engineering and Computer Science (SECS, volume 212)

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Table of contents (16 chapters)

  1. Front Matter

    Pages i-xv
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  2. A New Exact Minimizer for Two-Level Logic Synthesis

    • Robert K. Brayton, Patrick C. McGeer, Jagesh V. Sanghavi, Alberto L. Sangiovanni-Vincentelli
    Pages 1-31

  3. A New Graph Based Prime Computation Technique

    • O. Coudert, J. C. Madre
    Pages 33-57

  4. Logic Synthesizers, The Transduction Method and Its Extension, Sylon

    • Saburo Muroga
    Pages 59-86

  5. Network Optimization Using Don’t-Cares and Boolean Relations

    • Kuang-Chien Chen, Masahiro Fujita
    Pages 87-108

  6. Multi-Level Logic Minimization of Large Combinational Circuits by Partitioning

    • Masahiro Fujita, Yusuke Matsunaga, Yutaka Tamiya, Kuang-Chien Chen
    Pages 109-126

  7. A Partitioning Method for Area Optimization by Tree Analysis

    • Yuichi Nakamura, Kazutoshi Wakabayashi, Tomoyuki Fujita
    Pages 127-143

  8. A New Algorithm for 0-1 Programming Based on Binary Decision Diagrams

    • Seh-Woong Jeong, Fabio Somenzi
    Pages 145-165

  9. Delay Models and Exact Timing Analysis

    • Patrick C. McGeer, Alexander Saldanha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Pages 167-189

  10. Challenges to Dependable Asynchronous Processor Design

    • Takashi Nanya
    Pages 191-213

  11. Efficient Spectral Techniques for Logic Synthesis

    • Devadas Varma, E. A. Trachtenberg
    Pages 215-232

  12. FPGA Design by Generalized Functional Decomposition

    • Tsutomu Sasao
    Pages 233-258

  13. Logic Synthesis with Exor Gates

    • Tsutomu Sasao
    Pages 259-285

  14. And-Exor Expressions and their Optimization

    • Tsutomu Sasao
    Pages 287-312

  15. A Generation Method For Exor-Sum-of-Products Expressions Using Shared Binary Decision Diagrams

    • Koichi Yasuoka
    Pages 313-322

  16. A New Technology Mapping Method Based on Concurrent Factorization and Mapping

    • Minoru Inamori, Atsushi Takahara
    Pages 323-340

  17. Gate Sizing for Cell-Based Designs

    • Wei-Po Lee, Youn-Long Lin
    Pages 341-359

  18. Back Matter

    Pages 361-375
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Keywords

About this book

Logic Synthesis and Optimization presents up-to-date research information in a pedagogical form. The authors are recognized as the leading experts on the subject. The focus of the book is on logic minimization and includes such topics as two-level minimization, multi-level minimization, application of binary decision diagrams, delay optimization, asynchronous circuits, spectral method for logic design, field programmable gate array (FPGA) design, EXOR logic synthesis and technology mapping. Examples and illustrations are included so that each contribution can be read independently. Logic Synthesis and Optimization is an indispensable reference for academic researchers as well as professional CAD engineers.

Reviews

'....I would recommend this book to any graduate student, or practising digital system design engineer, who wishes to know more about the subject and perhaps even develop new algorithms of his or her own.' Microprocessors and Microsystems 18:8 1994

Editors and Affiliations

  • Kyushu Institute of Technology, Iizuka, Japan

    Tsutomu Sasao

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