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Design for High Performance, Low Power, and Reliable 3D Integrated Circuits

  • Book
  • © 2013

Overview

Authors:
  1. Sung Kyu Lim

    1. School of Electrical &, Computer Engineering, Georgia Institute of Technology, ATLANTA, USA

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  • Describes numerous “manufacturing-ready” GDSII-level layouts of TSV-based 3D ICs
  • Features sign-off level analysis of timing, power, signal integrity, and thermal analysis for 3D IC designs
  • Provides full details of all key algorithms, for maximum understanding and utility
  • Includes design-for-manufacturability (DFM), design-for-reliability (DFR), and design-for-testability (DFT) techniques that are considered critical to the physical design process
  • Includes supplementary material: sn.pub/extras

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Table of contents (20 chapters)

  1. Front Matter

    Pages i-xxviii
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  2. High Performance and Low Power 3D IC Designs

    1. Front Matter

      Pages 1-1
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    2. Regular Versus Irregular TSV Placement for 3D IC

      • Sung Kyu Lim
      Pages 3-40

    3. Steiner Routing for 3D IC

      • Sung Kyu Lim
      Pages 41-73

    4. Buffer Insertion for 3D IC

      • Sung Kyu Lim
      Pages 75-97

    5. Low Power Clock Routing for 3D IC

      • Sung Kyu Lim
      Pages 99-128

    6. Power Delivery Network Design for 3D IC

      • Sung Kyu Lim
      Pages 129-151

    7. 3D Clock Routing for Pre-bond Testability

      • Sung Kyu Lim
      Pages 153-185

  3. Electrical Reliability in 3D IC Designs

    1. Front Matter

      Pages 187-187
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    2. TSV-to-TSV Coupling Analysis and Optimization

      • Sung Kyu Lim
      Pages 189-203

    3. TSV Current Crowding and Power Integrity

      • Sung Kyu Lim
      Pages 205-229

    4. Modeling of Atomic Concentration at the Wire-to-TSV Interface

      • Sung Kyu Lim
      Pages 231-250

  4. Thermal Reliability in 3D IC Designs

    1. Front Matter

      Pages 251-251
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    2. Multi-objective Architectural Floorplanning for 3D IC

      • Sung Kyu Lim
      Pages 253-283

    3. Thermal-Aware Gate-Level Placement for 3D IC

      • Sung Kyu Lim
      Pages 285-308

    4. 3D IC Cooling with Micro-Fluidic Channels

      • Sung Kyu Lim
      Pages 309-341

  5. Mechanical Reliability in 3D IC Designs

    1. Front Matter

      Pages 343-343
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    2. Mechanical Reliability Analysis and Optimization for 3D ICs

      • Sung Kyu Lim
      Pages 345-378

    3. Impact of Mechanical Stress on Timing Variation for 3D IC

      • Sung Kyu Lim
      Pages 379-414

    4. Chip/Package Co-analysis of Mechanical Stress for 3D IC

      • Sung Kyu Lim
      Pages 415-441
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Keywords

About this book

This book provides readers with a variety of algorithms and software tools, dedicated to the physical design of through-silicon-via (TSV) based, three-dimensional integrated circuits. It describes numerous “manufacturing-ready” GDSII-level layouts of TSV-based 3D ICs developed with the tools covered in the book. This book will also feature sign-off level analysis of timing, power, signal integrity, and thermal analysis for 3D IC designs. Full details of the related algorithms will be provided so that the readers will be able not only to grasp the core mechanics of the physical design tools, but also to be able to reproduce and improve upon the results themselves. This book will also offer various design-for-manufacturability (DFM), design-for-reliability (DFR), and design-for-testability (DFT) techniques that are considered critical to the physical design process.

Authors and Affiliations

  • School of Electrical &, Computer Engineering, Georgia Institute of Technology, ATLANTA, USA

    Sung Kyu Lim

Bibliographic Information

  • Book Title: Design for High Performance, Low Power, and Reliable 3D Integrated Circuits

  • Authors: Sung Kyu Lim

  • DOI: https://doi.org/10.1007/978-1-4419-9542-1

  • Publisher: Springer New York, NY

  • eBook Packages: Engineering, Engineering (R0)

  • Copyright Information: Springer Science+Business Media New York 2013

  • Hardcover ISBN: 978-1-4419-9541-4

  • Softcover ISBN: 978-1-4899-8696-2

  • eBook ISBN: 978-1-4419-9542-1

  • Edition Number: 1

  • Number of Pages: XXVIII, 560

  • Topics: Circuits and Systems, Nanotechnology and Microengineering, Processor Architectures

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