Overview
- Editors:
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Chuan Seng Tan
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School Electrical & Electronic Eng., Photonics Res. Centre, Nanyang Technological University, Singapore, Singapore
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Ronald J. Gutmann
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Center for Integrated Electronics, Rensselaer Polytechnic Institute, Troy, U.S.A.
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L. Rafael Reif
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Dept. Electrical Engineering, Massachusetts Institute of Technology, Cambridge, U.S.A.
- Focuses on the foundry-based process technology for the fabrication of 3-D ICs
- Discusses the technology platform for pre-packaging wafer level 3-D ICs
- Includes chapters contributed by various experts in the field of wafer-level 3-D ICs process technology
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Table of contents (15 chapters)
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- Chuan Seng Tan, Ronald J. Gutmann, L. Rafael Reif
Pages 1-11
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- Christopher Petti, S. Brad Herner, Andrew Walker
Pages 1-17
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- Sharath Hosali, Greg Smith, Larry Smith, Susan Vitkavage, Sitaram Arkalgud
Pages 1-32
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- Kuan-Neng Chen, Chuan Seng Tan, Andy Fan, L. Rafael Reif
Pages 1-14
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- A. Munding, H. Hübner, A. Kaiser, S. Penka, P. Benkart, E. Kohn
Pages 1-39
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- James Burns, Brian Aull, Robert Berger, Nisha Checka, Chang-Lee Chen, Chenson Chen et al.
Pages 1-26
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- Anna W. Topol, Steven J. Koester, Douglas C. La Tulipe, Albert M. Young
Pages 1-21
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- Jian-Qiang Lu, Timothy S. Cale, Ronald J. Gutmann
Pages 1-38
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- Bart Swinnen, Anne Jourdain, Piet De Moor, Eric Beyne
Pages 1-11
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- Sheng-Chih Lin, Kaustav Banerjee
Pages 1-26
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- Scott K. Pozder, Robert E. Jones
Pages 1-20
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About this book
Three-dimensional (3D) integration is clearly the simplest answer to most of the semiconductor industry’s vexing problems: heterogeneous integration and red- tions of power, form factor, delay, and even cost. Conceptually the power, latency, and form factor of a system with a ?xed number of transistors all scale roughly linearly with the diameter of the smallest sphere enclosing frequently interacting devices. This clearly provides the fundamental motivation behind 3D technologies which vertically stack several strata of device and interconnect layers with high vertical interconnectivity. In addition, the ability to vertically stack strata with - vergent and even incompatible process ?ows provides for low cost and low parasitic integration of diverse technologies such as sensors, energy scavengers, nonvolatile memory, dense memory, fast memory, processors, and RF layers. These capabilities coupled with today’s trends of increasing levels of integrated functionality, lower power, smaller form factor, increasingly divergent process ?ows, and functional diversi?cation would seem to make 3D technologies a natural choice for most of the semiconductor industry. Since the concept of vertical integration of different strata has been around for over 20 years, why aren’t vertically stacked strata endemic to the semiconductor industry? The simple answer to this question is that in the past, the 3D advantages while interesting were not necessary due to the tremendous opportunities offered by geometric scaling. In addition, even when the global interconnect problem of high-performance single-core processors seemed insurmountable without inno- tions such as 3D, alternative architectural solutions such as multicores could eff- tivelydelaybutnoteliminatetheneedfor3D.
Editors and Affiliations
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School Electrical & Electronic Eng., Photonics Res. Centre, Nanyang Technological University, Singapore, Singapore
Chuan Seng Tan
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Center for Integrated Electronics, Rensselaer Polytechnic Institute, Troy, U.S.A.
Ronald J. Gutmann
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Dept. Electrical Engineering, Massachusetts Institute of Technology, Cambridge, U.S.A.
L. Rafael Reif
