Abstract
Power and energy consumed by a high-performance computing system are a significant problem nowadays. Superconducting computing technology may offer an attractive low-power alternative to traditional complementary metal–oxide–semiconductor (CMOS) technology due to the ultrafast and low power switching characteristics of superconductor devices. We offer a relatively comprehensive review of the latest development of superconducting computing technology from aspects of logic circuits, emerging superconducting architectures, and automated design tools. In light of the inner operation mechanisms, we classify the superconducting single flux quantum (SFQ) logic family into six major categories and discuss their respective strengths and weaknesses. Also, many novel superconducting architectures have been proposed, such as dual-clocks-based superconducting circuits, superconducting accelerators, and superconducting neuromorphic circuits. However, their effectiveness needs further evaluation, and their manufacturability is still unknown. Additional efforts are also demanded to enhance the electronic design automation of very large-scale integration (VLSI) SFQ circuits while maintaining a relatively low cost in area and power. We also discuss open challenges and future directions in the superconducting computing area of research.
Similar content being viewed by others
References
ABC.: A System for Sequential Synthesis and Verification. https://people.eecs.berkeley.edu/~alanmi/abc/ (2021)
Ando, Y., et al.: Design and demonstration of an 8-bit bit-serial RSFQ microprocessor: CORE e4. IEEE Trans. Appl. Supercond. 26, 1–5 (2016)
Armin, A., et al. Survey of stochastic computing. ACM Transactions on Embedded computing systems (TECS) 12 (2013)
Ayala, C. L., et al.: Mana: A monolithic adiabatic integration architecture microprocessor using 1.4-zj/op unshunted superconductor josephson junction devices. IEEE J. Solid-State Circ. 56, 1152–1165 (2021)
Bakolo, R. S., et al.: Analysis of a shielding approach for magnetic field tolerant SFQ circuits. IEEE Trans. Appl. Supercond. 27 (2017)
Bozbey, A., et al. Single flux quantum based ultrahigh speed spiking neuromorphic processor architecture. (2018)
Brandes, U., et al.: Fast and Simple Horizontal Coordinate Assignment. Graph Drawing, pp. 31–44. Berlin, Heidelberg (2002)
Brian, R.: Stochastic computing. Proceedings of the ACM spring joint computer conference (1967)
Bunyk, P. I., Rylov, S. V.: Automated calculation of mutual inductance matrices of multilayer superconductor integrated circuits. International superconductive electronics conference (ISEC) (1993)
Cai, R., et al.: A stochastic-computing based deep learning framework using adiabatic quantum-flux-parametron superconducting technology. In: Proceedings of the 46th International Symposium on Computer Architecture (ISCA) (2019a)
Cai, R., et al.: IDE Development. Logic synthesis and buffer/splitter insertion framework for adiabatic quantum-flux-parametron superconducting circuits. IEEE Computer Society Annual Symposium on VLSI (ISVLSI) (2019b)
Cai, R., et al.: A Buffer and splitter insertion framework for adiabatic quantum-flux-parametron superconducting circuits. IEEE 37th International Conference on Computer Design (ICCD) (2019c)
Chang, Y.C. et al.: ASAP: An Analytical Strategy for AQFP placement. IEEE/ACM International Conference On Computer Aided Design (ICCAD) (2020)
Chen, W., et al.: Rapid single flux quantum T-flip flop operating up to 770 GHz. IEEE Trans. Appl. Supercond. 2 (1999)
Cheng, P., et al.: Multi-terminal routing with length-matching for rapid single flux quantum circuits. Proceedings of the International Conference on Computer-Aided Design (2018)
Cheng, R., et al.: Superconducting neuromorphic computing using quantum phase-slip junctions. IEEE Trans. Appl. Supercond. 29, 1–5 (2019)
C3.: https://www.iarpa.gov/index.php/research-programs/c3 (2021)
de Villiers, J. F.: Automated Synthesis, Placement and Routing of Large-Scale RSFQ Integrated Circuits. Dissertation of Stellenbosch University (2021)
de Villiers, J. F.: Die2Sim. https://github.com/judefdiv/Die2Sim (2021)
JoSIM-Superconductor SPICE Simulator: Delport, J. A., Jackman, K., Roux, P. l., Fourie, C. J. IEEE Transactions on Applied Superconductivity 29, 1–5 (2019)
Dimov, B., et al.: Improved techniques for long-distance signal propagation within the rapid singleflux quantum digital circuits. Proc. Int. Symp. Signals Circ. Syst. 2 (2005)
Dorojevets, M., et al.: FLUX chip: design of a 20-GHz 16-bit ultrapipelined RSFQ processor prototype based on 1.75-/spl mu/m LTS technology. IEEE Trans. Appl. Supercond. 11, 326–332 (2001)
Fabrication.: Niobium integrated circuit fabrication. www.hypres.com/wp-content/uploads/2010/11/DesignRules-6.pdf (2021)
Fang, E. S., Van Duzer, T.: A Josephson integrated circuit simulator (JSIM) for superconductive electronics application. International superconductive electronics conference (ISEC) (1989)
Fayyazi, A., et al.: qEC: A Logical Equivalence Checking Framework Targeting SFQ Superconducting Circuits. IEEE International Superconductive Electronics Conference (ISEC) (2019)
Filippov, T., et al.: 8-Bit asynchronous wave-pipelined RSFQ arithmetic-logic unit. IEEE Trans. Appl. Supercond. 21, 847–851 (2011)
Fourie, C., et al.: Status of superconductor electronic circuit design software. IEEE Trans. Appl. Supercond. 23, 1300205–1300205 (2013)
Fourie, C., et al.: Digital superconducting electronics design tools - status and roadmap. IEEE Trans. Appl. Supercond. 28, 1–12 (2018)
Fourie, C. J., Wetzstein, O., Ortlepp, T., Kunert, J.: Three-dimensional multi-terminal superconductive integrated circuit inductance extraction. Supercond. Sci. Technol. 24, 125015 (2011)
Fourie, C.J.: Extraction of dc-biased SFQ circuit verilog models. IEEE Trans. Appl. Supercond. 28, 1–11 (2018)
Fu, R., et al.: Equivalence Checking for Superconducting RSFQ Logic Circuits. Proceedings of the 2021 on Great Lakes Symposium on VLSI (GLSVLSI) (2021). https://doi.org/10.1145/3453688.3461486
Fu, R. et al.: An Automatic placement algorithm for superconducting rapid single-flux-quantum logic circuits. IEEE Transactions on Applied Superconductivity. (2021)
Gaj, K., et al.: Tools for the computer-aided design of multigigahertz superconducting digital circuits. IEEE Trans. Appl. Supercond. 9, 18–38 (1999)
Gaj, K., Cheah, C.-H., Friedman, E.G., Feldman, M.J.: Functional modeling of RSFQ circuits using Verilog HDL. IEEE Trans. Appl. Superconduct. 7, 3151–3154 (1997)
Gaj, K., et al.: Timing of multi-gigahertz rapid single flux quantum digital circuits. High Performance Clock Distribution Networks. Springer. 135–164 (1997)
Ghasem, P., et al.: An efficient pipelined architecture for superconducting single flux quantum logic circuits utilizing dual clocks. In IEEE Transactions on Applied Superconductivity 30, 1–12 (2019)
Hansen, M.C., et al.: Unveiling the iscas-85 benchmarks: a case study in reverse engineering. IEEE Des. Test Comput. 16, 72–80 (1999)
Harnisch, T., Kunert, J., Toepfer, H., Uhlmann, H.F.: Design centering methods for yield optimization of cryoelectronic circuits. IEEE Trans. Appl. Supercond. 7, 3434–3437 (1997)
Herr, Q. P.: Single flux quantum circuits. US Patent 7724020. (2010)
Herr, Q.P., Feldman, M.J.: Multiparameter optimization of RSFQ circuits using the method of inscribed hyperspheres. IEEE Trans. Appl. Superconduct. 5, 3337–3340 (1995)
Holmes, D.S., et al.: Energy-efficient superconducting computing-power budgets and requirements. IEEE Trans. Appl. Supercond. 23, 1701610–1701610 (2013)
Holmes, D., et al.: Superconducting computing in large-scale hybrid systems. Computer 48, 34–42 (2015)
IARPA SuperTools Program.: https://www.iarpa.gov/index.php/research-rograms/supertools (2018)
Igor, I., et al.: Beyond Moore’s technologies: operation principles of a superconductor alternative. Beilstein J. Nanotechnol. 8, 2689–2710 (2017)
Intelligent Design of Electronic Assets.:www.darpa.mil/program/intelligent-design-of-electronic-assets (2021)
Ishida, K., et al.: 32 GHz 6.5 mW gate-level-pipelined 4-bit processor using superconductor single-flux-quantum logic. IEEE Symposium on VLSI Circuits (2020a)
Ishida, K., et al.: Supernpu: An extremely fast neural processing unit using superconducting logic devices. 2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO). IEEE, 2020
Jackman, K., et al.: Flux trapping experiments to verify simulation models. Supercond. Sci. Technol. 33, 105001 (2020)
Jouppi, N. P., et al.: In-datacenter performance analysis of a tensor processing unit. Proceedings of the 44th Annual International Symposium on Computer Architecture (ISCA) (2017). https://doi.org/10.1145/3079856.3080246
Kameda, Y., et al.: Automatic Josephson-transmission-line routing for single-flux-quantum cell-based logic circuits. IEEE Trans. Appl. Supercond. 13, 519–522 (2003)
Kameda, Y., et al.: A new design methodology for single-flux-quantum (SFQ) logic circuits using passive-transmission-line (PTL) wiring. IEEE Trans. Appl. Supercond. 17, 508–511 (2007)
Kameda, Y., Yorozu, S., Hashimoto, Y.: Automatic single-flux-quantum (SFQ) logic synthesis method for top-down circuit design. J. Phys: Conf. Ser. 43, 1179–1182 (2006)
Kamon, M., Tsuk, M.J., White, J.K.: FASTHENRY: a multipole-accelerated 3-D inductance extraction program. IEEE Trans. Microw. Theory Tech. 42, 1750–1758 (1994)
Kang, J., et al.: Current recycling and SFQ signal transfer in large scale RSFQ circuits. IEEE Trans. Appl. Supercond. 13, 547–550 (2003)
Katam, N. et al.: Ground plane partitioning for current recycling of superconducting circuits. Design, Automation & Test in Europe Conference & Exhibition (DATE) (2020). https://doi.org/10.23919/DATE48585.2020.9116557
Katam, N., Shafaei, A., Pedram, M.: Design of complex rapid single-flux-quantum cells with application to logic synthesis. In: 16th International Superconductive Electronics Conference (ISEC) (2017)
Khapaev, M.M., Kidiyarova-Shevchenko, A.Y., Magnelind, P., Kupriyanov, M.Y.: 3D-MLSI: software package for inductance calculation in multilayer superconducting integrated circuits. IEEE Trans. Appl. Supercond. 11, 1090–1093 (2001)
Kito, N., et al.: A fast wire-routing method and an automatic layout tool for RSFQ digital circuits considering wire-length matching. IEEE Trans. Appl. Supercond. 28, 1–5 (2018)
Kito, N., et al.: Automatic wire-routing of SFQ digital circuits considering wire-length matching. IEEE Trans. Appl. Supercond. 26, 1–5 (2016)
Kleiner, R., et al.: Superconducting quantum interference devices: state of the art and applications. Proc. IEEE 92, 1534–1548 (2004)
Kondo, T., et al.: Design and implementation of stochastic neurosystem using SFQ logic circuits. IEEE Trans. Appl. Supercond. 15, 320–323 (2005)
Krasniewski, A.: Logic simulation of RSFQ circuits. IEEE Trans. Appl. Superconduct. 3, 33–38 (1993)
Krylov, G. et al.: Design methodology for distributed large scale ERSFQ bias networks. IEEE Trans. Very Large Scale Integration (VLSI) Syst.. 28(11), 2438–2447 (2020)
Krylov, G. et al.: Partitioning RSFQ circuits for current recycling. IEEE Transactions on Applied Superconductivity, (2021)
Lee, S. et al.: Irredundant buffer and splitter insertion and scheduling-based optimization for AQFP circuits. 30th International Workshop on Logic & Synthesis (IWLS) (2021)
Li, G., et al.: Fabrication and characterization of superconducting RSFQ circuits. Rare Met. 38, 899–904 (2019)
Likharev, K.K., et al.: RSFQ logic/memory family: a new Josephson-junction technology for sub-terahertz-clock-frequency digital systems. IEEE Trans. Appl. Supercond. 1, 3–28 (1991)
Lin, T., et al.: qGDR: a via-minimization-oriented routing tool for large-scale superconductive single-flux-quantum circuits. IEEE Trans. Appl. Supercond. 29, 1–12 (2019)
Lin, T. R., Pedram, M.: Retiming for high-performance superconductive circuits with register energy minimization. IEEE/ACM International Conference on Computer-Aided Design (ICCAD) (2020)
Lin, Y. et al.: DREAMPlace: deep learning toolkit-enabled GPU acceleration for modern VLSI placement. In: 56th ACM/IEEE Design Automation Conference (DAC) (2019)
Magic VLSI Layout Tool.: http://opencircuitdesign.com/magic/index.html (2021)
Mauritsen L., et al.: Low vibration, low thermal fluctuation system for pulse tube and Gifford-McMahon cryocoolers. Cryocoolers 15, Boulder: ICC Press, 581–585 (2009)
Michael, L., et al.: High-speed low-power neuromorphic systems based on magnetic Josephson junctions. J. Appl. Phys. (2018). https://doi.org/10.1063/1.5042425
Mukhanov, O.A., et al.: Energy-efficient single ux quantum technology. IEEE Trans. Appl. Supercond. 21, 760–769 (2011)
Munir, M., et al.: qMC: a formal model checking verification framework for superconducting logic. In: Proceedings of the 2021 on Great Lakes Symposium on VLSI (GLSVLSI) (2021)
Murai, Y., et al.: Development and demonstration of a post-placement routing approach for large-scale adiabatic quantum-flux-parametron circuits using channel routing. Proc. IEICE Tech. Rep. 116, 7–12 (2016)
Murai, Y., et al.: Development and demonstration of routing and placement EDA tools for large-scale adiabatic quantum-flux-parametron circuits. IEEE Trans. Appl. Supercond. 27, 1–9 (2017)
Nagaoka, I., et al.: A 48GHz 5.6mW gate-level-pipelined multiplier using single-flux quantum logic. In: 2019 IEEE International Solid-State Circuits Conference (ISSCC) (2019)
Nagaoka, I., et al.: Demonstration of a 52-GHz bit-parallel multiplier using low-voltage rapid single-flux-quantum logic. IEEE Trans. Appl. Supercond. 31, 1–5 (2021)
Narama, T. et al.: Demonstration of 10k gate-scale adiabatic-quantum-fluxparametron circuits. In 15th International Superconductive Electronics Conference (ISEC) (2015)
Naoki, T. et al.: Measurement of 10 zJ energy dissipation of adiabatic quantum-flux parametron logic using a superconducting resonator. Appl. Phys. Lett. 102 (2013)
Oberg, O.T., et al.: Integrated power divider for superconducting digital circuits. IEEE Trans. Appl. Supercond. 21, 571–574 (2011)
Onomi, T., et al.: An improved superconducting neural circuit and its application for a neural network solving a combinatorial optimization problem. J. Phys. Conf. 507, 042029 (2014)
Pasandi, G.: Designing efficient algorithms and developing suitable software tools to support logic synthesis of superconducting single flux quantum circuits. Dissertation of University of Southern California, Los Angeles (2020a)
Pasandi, G., Pedram, M.: A graph partitioning algorithm with application in synthesizing single flux quantum logic circuits. CoRR (2018)
Pasandi, G., et al.: Depth-bounded graph partitioning algorithm and dual clocking method for realization of superconducting SFQ Circuits. J. Emerg. Technol. Comput. Syst. 17 (2020b)
Pasandi, G. et al.: SFQmap: a technology mapping tool for single flux quantum logic circuits. International Symposium on Circuits and Systems (ISCAS) (2018)
Pasandi, G., et al.: PBMap: a path balancing technology mapping algorithm for single flux quantum logic circuits. IEEE Trans. Appl. Supercond. 29, 1–14 (2019)
Pasandi, G. et al.: Balanced Factorization and Rewriting Algorithms for Synthesizing Single Flux Quantum Logic Circuits. Proceedings of the 2019 on Great Lakes Symposium on VLSI (2019)
Pasandi, G. et al.: qSeq: full algorithmic and tool support for synthesizing sequential circuits in superconducting SFQ technology. 2021 58th ACM/IEEE Design Automation Conference (DAC) (2021)
Polonsky, S.V., et al.: Transmission of single-flux-quantum pulses along superconductingmicrostrip lines. IEEE Trans. Appl. Supercond. 3, 2598–2600 (1993)
Polonsky, S., Shevchenko, P., Kirichenko, A., Zinoviev, D., Rylyakov, A.: PSCAN’96: new software for simulation and optimization of complex RSFQ circuits. IEEE Trans. Appl. Supercond. 7, 2685–2689 (1997)
Qrouter.: http://opencircuitdesign.com/qrouter/index.html (2021)
Radebaugh, R.: Review of refrigeration methods. Handbook of Superconducting Materials, 2nd edition, D.A. Carwell and D. Larbalestier editors, Taylor and Francis Books (2020)
Russek, S., et al.: Stochastic Single Flux Quantum Neuromorphic Computing using Magnetically Tunable Josephson Junctions. IEEE International Conference on Rebooting Computing (ICRC) (2016)
Saito, R., et al.: Logic synthesis of sequential logic circuits for adiabatic quantum-flux-parametron logic. IEEE Trans. Appl. Supercond. 31, 1–5 (2021)
Sander, G.: Layout of Directed Hypergraphs with Orthogonal Hyperedges. Graph Drawing, pp. 381–386. Berlin, Heidelberg (2004)
Schindler, L.: The development and characterisation of a parameterised RSFQ cell library for layout synthesis, Doctoral dissertation, Stellenbosch University (2021)
Schneider, M., et al.: Ultralow power artificial synapses using nanotextured magnetic Josephson junctions. Science Adv. 4, e1701329, (2018a). https://doi.org/10.1126/sciadv.1701329
Schneider, M., et al.: Tutorial: High-speed low-power neuromorphic systems based on magnetic Josephson junctions. J. Appl. Phys. 124, 161102 (2018b)
Segall, K., et al.: Synchronization dynamics on the picosecond time scale in coupled Josephson junction neurons. Phys. Rev. E 95, 032220 (2017)
Semenov, V. K., et al.: How moats protect superconductor films from flux trapping. IEEE Trans. Appl. Supercond. 26 (2016)
Semenov, V., et al.: Current recycling: New results. IEEE Trans. Appl. Supercond. 29 (2019)
Shahsavani, S., et al.: Accurate margin calculation for single flux quantum logic cells. Design, Automation & Test in Europe Conference & Exhibition (DATE) (2018a)
Shahsavani, S., et al.: An integrated row-based cell placement and interconnect synthesis tool for large SFQ logic circuits. IEEE Trans. Appl. Supercond. 27, 1–8 (2017)
Shahsavani, S., et al.: A placement algorithm for superconducting logic circuits based on cell grouping and super-cell placement. Design, Automation & Test in Europe Conference & Exhibition (DATE) (2018b)
Shahsavani, S.N., et al.: A minimum-skew clock tree synthesis algorithm for single flux quantum logic circuits. IEEE Trans. Appl. Supercond. 29, 1–13 (2019)
Shahsavani, S. N., et al.: A timing uncertainty-aware clock tree topology generation algorithm for single flux quantum circuits. Design, Automation & Test in Europe Conference & Exhibition (DATE) (2020)
Supercomputer.: https://www.top500.org/lists/top500/2021/06/ (2021)
Tadros, R.N.: Clocking Solutions for SFQ Circuits. Dissertations of University of Southern California (2019)
Takagi, K., et al.: SFQ propagation properties in passive transmission lines based on a 10-nb-layer structure. IEEE Trans. Appl. Supercond. 19, 617–620 (2009)
Takeuchi, N., et al.: An adiabatic quantum flux parametron as an ultra-low-power logic device. Superconductor Science and Technology 26, 035010 (2013)
Takeuchi, N., et al.: An adiabatic superconductor 8-bit adder with 24kbt energy dissipation per junction. Appl. Phys. Lett. 114, 042602 (2019). https://doi.org/10.1063/1.5080753
Takeuchi, N., Yamanashi, Y., Yoshikawa, N.: Adiabatic quantum-flux-parametron cell library adopting minimalist design. J Appl Phys 117, 173912 (2015)
Takeuchi, N., et al.: Adiabatic quantum-flux-parametron cell library designed using a 10 kA cm−2 niobium fabrication process. Supercond Sci Technol. 30(3), 035002 (2017)
Takeuchi, N., et al.: Scalable readout interface for superconducting nanowire single-photon detectors using AQFP and RSFQ logic families. Opt. Express 28(11), 15824–15834 (2020)
Tanaka, M., et al.: Low-energy consumption RSFQ circuits driven by low voltages. IEEE Trans. Appl. Supercond. 23, 1701104–1701104 (2013). https://doi.org/10.1109/TASC.2013.2240555
Tanaka, M., et al.: Automated passive-transmission-line routing tool for single-flux-quantum circuits based on A* Algorithm. IEICE Transactions. 93-C, 435–439 (2010)
Tanaka, T., et al.: Fabrication of adiabatic quantum-flux-parametron integrated circuits using an automatic placement tool based on genetic algorithms. IEEE Trans. Appl. Supercond. 29(5), 1–6 (2019)
Tang, G., et al.: Logic design of a 16-bit bit-slice arithmetic logic unit for 32-/64-bit RSFQ microprocessors. IEEE Trans. Appl. Supercond. 28, 1–5 (2018)
Tang, G., et al.: 4-bit bit-slice arithmetic logic unit for 32-bit rsfq microprocessors. IEEE Trans. Appl. Supercond. 26, 1–6 (2016)
Terai, H., et al.: Design and testing of SFQ signal processor for 64-pixel SSPD array. The Applied Superconductivity Conference (ASC) (2014)
ter Brake, H.J.M., et al.: SCENET roadmap for superconductor digital electronics. Physica C 439, 1–41 (2006)
Testa, E., et al.: Algebraic and Boolean Optimization Methods for AQFP Superconducting Circuits. 22nd Asia and South Pacific Design Automation Conference (ASP-DAC) (2021)
Tolpygo, S.K.: Superconductor digital electronics: Scalability and energy efficiency issues. Low Temp. Phys. 42, 361–379 (2016b)
Tsuji, N., et al.: Design and implementation of a 16-word by 1-bit register file using adiabatic quantum flux parametron logic. IEEE Trans. Appl. Supercond. 27, 1–4 (2017)
Tzimpragos, G., et al.: Superconducting Computing with Alternating Logic Elements. ACM/IEEE 48th Annual International Symposium on Computer Architecture (ISCA) (2021)
Van, D., et al.: Principles of superconductive devices and circuits. Edward Arnold, United Kingdom (1981)
Tzimpragos, G., et al., Temporal computing with superconductors. IEEE Micro. (2021)
Tzimpragos, G., et al.: A computational temporal logic for superconducting accelerators. Proceedings of the Twenty-Fifth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS) (2020). https://doi.org/10.1145/3373376.3378517
Vernik, I., et al.: Experimental investigation of local timing parameter variations in RSFQ circuits. IEEE Trans. Appl. Supercond. 9, 4341–4344 (1999)
Weste, N., et al.: CMOS VLSI Design: A Circuits and Systems Perspective. Addison Wesley Publishing Company Incorporated. (2011)
Whiteley, S.R.: Josephson junctions in SPICE3. IEEE Trans. Magn. 27, 2902–2905 (1991)
Whiteley, S. R.: Xictools. https://github.com/wrcad/xictools (2019)
Wong, A. D., et al.: VeriSFQ-A semi-formal verification framework and benchmark for single flux quantum technology. In: International Symposium on Quality Electronic Design (ISQED) (2019)
Xie, Z., et al.: RouteNet: routability prediction for mixed-size designs using convolutional neural network. In: IEEE/ACM International Conference on Computer-Aided Design (ICCAD) (2018)
Xu, Q., et al.: Synthesis flow for cell-based adiabatic quantum-flux-parametron structural circuit generation with HDL back-end verification. IEEE Trans. Appl. Supercond. 27, 1–5 (2017)
Yamada, T., et al.: Flexible superconducting passive interconnects with 50-Gb/s signal transmissions in single-flux-quantum circuits. Jpn J. Appl. Phys. 45, 752–757 (2006)
Yamanashi, Y., et al.: Design and implementation of a pipelined bit-serial SFQ microprocessor, CORE 1β. IEEE Trans. Appl. Supercond. 17, 474–477 (2007a)
Yamanashi, Y., et al.: Study of LR-loading technique for low-power single flux quantum circuits. IEEE Trans. Appl. Supercond. 17, 150–153 (2007b). https://doi.org/10.1109/TASC.2007.898608
Yamanashi, Y., et al.: Pseudo sigmoid function generator for a superconductive neural network. IEEE Trans. Appl. Supercond. (2013). https://doi.org/10.1109/TASC.2012.2228531
Yamashita, S., Tanaka, K., Takada, H., et al.: A transduction-based framework to synthesize RSFQ circuits. Asia and South Pacific Conference on Design Automation (2006)
Yamazaki, Y., et al.: A compact interface between adiabatic quantum-flux-parametron and rapid single-flux-quantum circuits. IEEE Trans. Appl. Supercond. 31, 1–5 (2021). https://doi.org/10.1109/TASC.2021.3072002
Yan, J.: Length-matching-constrained region routing in rapid single-flux-quantum circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, (2020)
Yan, J.: Via-minimization-oriented region routing under length-matching constraints in rapid single-flux-quantum circuits. IEEE Trans. Very Large Scale Integration (VLSI) Syst. 29, 1257–1270 (2021)
Yoshikawa, N., Koshiyama, J.: Top-down RSFQ logic design based on a binary decision diagram. IEEE Trans. Appl. Supercond. 11, 1098–1101 (2001)
Yoshikawa, N., et al.: Reduction of power consumption of RSFQ circuits by inductance-load biasing. Supercond. Sci. Technol. 12, 918–920 (1999)
Yu, W., et al.: A survey on the edge computing for the internet of thing. IEEE Access. 6, 6900–6919 (2018)
Zhang, G., et al.: Circuit-GNN: Graph Neural Networks for Distributed Circuit Design. Proceedings of the 36th International Conference on Machine Learning (2019)
Zhu, K., et al.: Exploring Logic Optimizations with Reinforcement Learning and Graph Convolutional Network. Proceedings of the 2020 ACM/IEEE Workshop on Machine Learning for CAD (2020)
Zhu, J., et al.: A comprehensive review on emerging artificial neuromorphic devices. Appl. Phys. Rev. 7, 011312 (2020)
Acknowledgements
This work was supported in part by the Strategic Priority Research Program of the Chinese Academy of Sciences under Grant XDA18000000; and in part by the National Natural Science Foundation of China under Grant 61732018, 61872335, 61802367.
Author information
Authors and Affiliations
Corresponding author
Rights and permissions
About this article
Cite this article
Huang, J., Fu, R., Ye, X. et al. A survey on superconducting computing technology: circuits, architectures and design tools. CCF Trans. HPC 4, 1–22 (2022). https://doi.org/10.1007/s42514-022-00089-w
Received:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s42514-022-00089-w