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Improvement of Multilevel Inverters Topology Using Series and Parallel Connections of DC Voltage Sources

  • Research Article - Electrical Engineering
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Abstract

This paper proposes a new topology for multilevel inverters based on series and parallel {R1–7} connection’s of the dc voltage sources. Series and parallel {R1–7} connections ability of the proposed topology make it capable of increasing the number of voltage levels and the output current, respectively. The proposed topology is optimized from the viewpoint of number of switches, number of dc voltage sources, and maximum blocked voltage by switches. The optimal topologies with minimum number of switches and dc voltage sources are computed to produce the maximum number of output voltage levels with minimum blocked voltage by switches. In addition, a new algorithm for the determination of magnitudes of dc voltage sources is presented. Furthermore, to verify the theoretical aspects, the proposed topology is compared with some of the new presented multilevel inverters. The performance of the proposed multilevel inverter is verified by the simulation and experimental results of a single-phase 25-level inverter.

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Abbreviations

V dc :

Isolated dc voltage source

m :

Number of dc voltage sources connected in parallel

n :

Number of dc voltage sources for the extended unit

n j :

Number of dc voltage sources for the jth unit

N step,j :

Number of voltage levels for the jth unit

V j :

Magnitude of dc voltage source used in jth unit

v o :

Output voltage

v o,j :

Output voltage of the jth unit

V o, max :

Maximum output voltage

I j :

Nominal current of the dc voltage source used in jth unit

I o, j :

Nominal output current of jth unit

k :

Number of units

N IGBT :

Number of IGBTs

N step :

Number of voltage levels

N dc :

Number of dc voltage sources

V switch :

Standing voltage

V switch,j :

Standing voltage of jth unit

c :

Constant value

\({C_{k}^{m}}\) :

Number of mcombinations from k numbers

R :

Load resistance

L :

Load inductance

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Authors and Affiliations

  1. Faculty of Electrical and Computer Engineering, University of Tabriz, Tabriz, Iran

    Ebrahim Babaei, Saeed Sheermohammadzadeh & Mehran Sabahi

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  1. Ebrahim Babaei
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  2. Saeed Sheermohammadzadeh
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  3. Mehran Sabahi
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Correspondence to Ebrahim Babaei.

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Babaei, E., Sheermohammadzadeh, S. & Sabahi, M. Improvement of Multilevel Inverters Topology Using Series and Parallel Connections of DC Voltage Sources. Arab J Sci Eng 39, 1117–1127 (2014). https://doi.org/10.1007/s13369-013-0696-9

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  • DOI: https://doi.org/10.1007/s13369-013-0696-9

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