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Handling Unknown with Blend of Scan and Scan Compression

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Abstract

In scan compression, all scannable Flip-Flops are part of internal scan channels connected between Decompressor and Compressor. The capture-X (unknown values in the test response) in the Flip-Flops after capture cycle of scan synthesis, results in loss of coverage and/or pattern inflation when masking is used to block the Xs irrespective of the X-masking techniques used in scan compression. In this paper, we exploited this potential and propose a hybrid DFT (Design For Testability) architecture to achieve better compression and reduce patterns count. This is a mixture of an external scan chain and scan compression. A methodology has been put in place based on the potential of a capture-X value of occurring in Flip-Flips, to find out which Flip-Flops (scan cells) should be part of the internal scan channels (chains) between Decompressor and Compressor, and which Flip-Flops should be put outside the codec (Compressor-Decompressor) as an external scan chain. The results show the benefits of the hybrid architecture which is shown to bring significant improvement in pattern count.

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Authors and Affiliations

  1. Department of Computer Science, Jain University, Bengaluru, India

    Pralhadrao V. Shantagiri

  2. Research Guide, Jain University, Bengaluru, India

    Rohit Kapur

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  1. Pralhadrao V. Shantagiri
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  2. Rohit Kapur
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Correspondence to Pralhadrao V. Shantagiri.

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Responsible Editor: N. A. Touba

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Shantagiri, P.V., Kapur, R. Handling Unknown with Blend of Scan and Scan Compression. J Electron Test 34, 135–146 (2018). https://doi.org/10.1007/s10836-018-5717-x

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  • DOI: https://doi.org/10.1007/s10836-018-5717-x

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