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New Light Weight Threshold Voltage Defined Camouflaged Gates for Trustworthy Designs

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Abstract

The outsourcing of the IC fabrication process introduces the security vulnerabilities into the design. An attacker can exploit them to extract the functionality using image processing-based reverse engineering and can also mount the various attacks such as hardware Trojan, piracy, overbuilding, etc. Various dummy contacts and Threshold Voltage Defined (TVD) logic-based layout camouflaging techniques are presented that can deceive the attacker into incorrectly interpreting the functionality of the camouflaged gate. The existing dummy contact-based techniques require large overhead and provide poor security whereas, the TVD logic-based camouflaging techniques increase the security at the cost of large area and energy overhead. Therefore, in this paper, new light weight TVD static and dynamic logic (TVD-SL and TVD-DL) based camouflaged gates are proposed. The proposed TVD-SL/DL gates have same physical structure and provide the functionality of several standard gates by implanting different threshold voltages during manufacturing. Further, various simplified TVD-SL/DL gates are also proposed to achieve the overhead and security trade-off. To evaluate the efficacy, the proposed TVD logic gates are implemented using 32nm PTM library and simulated using the HSPICE simulator. The simulation results show that the proposed TVD-SL-based gates on an average reduce 35.49%, 59.18% and 72.05% whereas the proposed TVD-DL reduces 54.84%, 84.18% and 82.30% area, power and delay respectively over the existing. Further, on an average, the proposed TVD-DL-based camouflaged gates require 56% less power over the standard gates. Due to the low-cost and high energy efficiency, the proposed logic gates are best suited for the development of secure and portable devices for the Internet of Things applications.

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Authors and Affiliations

  1. ABV- Indian Institute of Information Technology and Management, Gwalior, India

    Vijaypal Singh Rathor, Bharat Garg & G. K. Sharma

Authors
  1. Vijaypal Singh Rathor
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  2. Bharat Garg
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  3. G. K. Sharma
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Correspondence to Vijaypal Singh Rathor.

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Responsible Editor: S. Bhunia

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Rathor, V.S., Garg, B. & Sharma, G.K. New Light Weight Threshold Voltage Defined Camouflaged Gates for Trustworthy Designs. J Electron Test 33, 657–668 (2017). https://doi.org/10.1007/s10836-017-5683-8

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  • DOI: https://doi.org/10.1007/s10836-017-5683-8

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