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Power-Aware Optimization of SoC Test Schedules Using Voltage and Frequency Scaling

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Abstract

With shrinking device sizes, System-on-Chip (SoC) cores are growing in number and complexity. This has led to high volumes of test data and long test times. Therefore, reducing test cost by minimizing the overall test time is one of the main goals of SoC testing. To efficiently manage test resources and power dissipation, tests for the SoC cores are arranged into test schedules. Traditional SoC test methods assume a constant test frequency and supply voltage (V D D ) for the entire test schedule. However, test power and test time can be regulated by varying V D D and test clock frequency to optimize SoC test schedules for a given power budget. The research presented in this paper focuses on power-aware optimization of SoC test schedules to minimize test time by scaling the supply voltage and test clock rate. This scaling can be on a per session basis (in case of session-based test schedules) or dynamically (in case of sessionless test schedules). Exact and heuristic algorithms for solving the optimization problem are discussed. These algorithms are implemented and applied to several SoC benchmarks. Results show a significant reduction in SoC test time over the conventional test schedules where V D D and clock are fixed at given nominal values.

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Acknowledgments

Authors are grateful to the National Science Foundation for Grants CCF-1116213, IIP-0738088 and IIP-1266036. They express gratitude to Dr. Spencer Millican and Prof. Kewal Saluja, University of Wisconsin, Madison, for providing power profiles for ITC’02 benchmarks. They thank Erik Jan Marinissen, IMEC, Belgium, and Prof. Nicola Nicolici, McMaster University, Canada, for their valuable inputs on sessionless and session-based test scheduling, and Prof. Alice Smith, Auburn University, for guidance on optimization heuristics.

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  1. Vijay Sheshadri

    Present address: Intel Corporation, Hillsboro, OR, 97124, USA

Authors and Affiliations

  1. Department of Electrical and Computer Engineering, Auburn University, Auburn, AL, 36849, USA

    Vijay Sheshadri, Vishwani D. Agrawal & Prathima Agrawal

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  1. Vijay Sheshadri
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  2. Vishwani D. Agrawal
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Correspondence to Vishwani D. Agrawal.

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Responsible Editor: K. K. Saluja

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Sheshadri, V., Agrawal, V.D. & Agrawal, P. Power-Aware Optimization of SoC Test Schedules Using Voltage and Frequency Scaling. J Electron Test 33, 171–187 (2017). https://doi.org/10.1007/s10836-017-5652-2

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