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High performance 9T adiabatic SRAM and novel stability characterization using pole zero placement

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Abstract

Stability of memory cells always considered as a most significant figure for defining the logic data at output terminals. And the value of logic data is influenced due to the dominance of leakage component at deep submicron technology. Stability analysis and leakage issues of new 9T adiabatic static random access memory (SRAM) cells is presented using the technique of pole zero concept. With the help of flow graph characteristic of memory cell is modeled and validated using MATLAB tool. The elementary cell of proposed SRAM resembles behavior of 4T-SRAM consisting of two high load resistors constructed of PMOS and cross-coupled NMOS pair. NMOS switch is used to restrict short circuit current and two gradually rising and falling wave pulses with controlled switching current flow. The simulation is carried out at 180 nm technology and it has been found that the average power dissipation of the proposed SRAM reduces by a factor of 41 with no performance degradation and energy is efficiently recovered using adiabatic and body biasing technique.

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Authors and Affiliations

  1. Electronics Engineering Department, YMCA University of Science and Technology, Faridabad, Haryana, India

    Sunil Jadav

  2. Electronics and Communication Engineering, National Institute of Technology, Hamirpur, Hamirpur, Himachal Pradesh, India

    Rajeevan Chandel

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  1. Sunil Jadav
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  2. Rajeevan Chandel
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Correspondence to Sunil Jadav.

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Jadav, S., Chandel, R. High performance 9T adiabatic SRAM and novel stability characterization using pole zero placement. Analog Integr Circ Sig Process 98, 347–355 (2019). https://doi.org/10.1007/s10470-018-1308-0

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  • DOI: https://doi.org/10.1007/s10470-018-1308-0

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