Skip to main content
SpringerLink
Log in

Effect of PVT variations on differential-time signaling data link architecture

  • Published:
Analog Integrated Circuits and Signal Processing Aims and scope Submit manuscript

Abstract

In this paper, the effect of process, voltage and temperature (PVT) variation on the differential-time signaling (DTS) serial link architecture has been studied. An example of 65 nm CMOS 4-bit 6 Gb/s DTS serial link has been designed and simulated using 1.5 GHz as an input clock signal in order to study the effect of PVT variation on DTS architectures. Mont-Carlo simulations have been carried out for the designed link. The simulated link has been tested under different operating temperatures from 0 to 120 °C, the link achieves correct transmission for the temperature range from 0 to 80 °C without calibrating the delay lines against the temperature change. The voltage supply has been varied from 0.95 to 1.05 V in order to study the effect of the voltage supply variation. The simulated link achieves correct transmission for a voltage supply variation within ± 2.5% of the nominal value without calibrating the delay lines against the voltage supply change. Using the DTS architecture as a serial link tolerate an adequate amount of PVT variation as well as relaxes the design constrains of the calibration technique, which is required for the delay lines to ensure correct transmission.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13
Fig. 14
Fig. 15
Fig. 16
Fig. 17

Similar content being viewed by others

References

  1. Bea, W., Yoo, B. -J., & Jeong, D. -K. (2012). Design of CMOS 5 Gb/s 4-PAM transceiver frontend for low-power memory interfave. In IEEE international SoC design conference (ISOCC) (pp. 49–52).

  2. Fukuda, K., et al. (2010). A 12.3 mW 12.5 Gb/s complete transceiver in 65 nm CMOS. In International solid-state circuits conference (ISSCC), San Francisco, USA (pp. 368–369).

  3. Gangasani, G. R., et al. (2014). A 32 Gb/s backplane transceiver with on-chip AC-coupling and low latency CDR in 32 nm SOI CMOS technology. IEEE Journal of Solid-State Circuits (JSSC), 49(11), 2474–2489.

    Article  Google Scholar 

  4. Bulzacchelli, J. F. (2013). Design techniques for CMOS backplane transceivers approaching 30-Gb/s data rates. In IEEE custom integrated circuits conference (CICC), San Jose, CA, USA, 22–25 September 2013 (pp. 1–8).

  5. Kimura, H., et al. (2014). A 28 Gb/s 560 mW multi-standard SerDes with single-stage analog front-end and 14-tap decision feedback equalizer in 28 nm CMOS. IEEE Journal of Solid-State Circuits Journal (JSSC), 49(12), 3091–3103.

    Article  Google Scholar 

  6. Harwood, M. et al., (2012). A 225 mW 28 Gb/s SerDes in 40 nm CMOS with 13 dB of analog equalization for 100GBASE-LR4 and optical transport lane 4.4 applications. In International solid-state circuits conference (ISSCC), San Francisco, USA (pp. 326–327).

  7. Zhang, C., et al. (2013). Multi-channel 5 Gb/s/ch SERDES with emphasis on integrated novel clocking strategies. Journal of Semiconductor Technology and Science, 13(4), 303–317.

    Article  Google Scholar 

  8. Song, B., et al. (2013). A CMOS 7 Gb/s, 4-PAM and 4-PWM, serial link transceiver. IEEE Transaction on Circuits and Systems I, Regular Papers (TCAS-I), 60(2), 457–468.

    Article  Google Scholar 

  9. Ghaderi, N., Ghol, Z., & Fatemi, S. (2016). A CMOS 7 Gb/s, 4-PAM and 4-PWM, serial link transceiver. Analog Integrated Circuits and Signal Processing, 89(3), 809–823.

    Article  Google Scholar 

  10. Rashdan, M. (2017). Dual-time resolution time-based transceiver for low-power serial interfaces. Analog Integrated Circuits and Signal Processing, 92(1), 81–89.

    Article  Google Scholar 

  11. Rashdan, M., Yousif, A., Haslett, J. W., & Maundy, B. (2012). Differential time-signaling data-link architecture. Journal of Signal Processing Systems, 70(1), 21–37.

    Article  Google Scholar 

  12. Rashdan, M., Yousif, A., Haslett, J., & Maundy, B. (2009). A new time-based architecture for serial communication links. In IEEE 16th international conference on electronics Hammamat: Circuits and systems (ICECS) (pp. 531–534).

  13. Townsend, K. (2010). Interference-mitigating TR-UWB receiver. Ph.D. thesis. Calgary, Alberta: University of Calgary.

  14. Sedra, A. S., & Smith, K. C. (2004). Microelectronic circuits (4th ed.). New York: Oxford University Press.

    Google Scholar 

  15. Abidi, A. (2006). Phase noise and jitter in CMOS ring oscillators. IEEE Journal of Solid State Circuits, 41(8), 1803–1816.

    Article  Google Scholar 

  16. Townsend, K. A., Macpherson, A. R., & Haslett, J. (2010). A fine-resolution time-to-digital converter for a 5Gs/s ADC. In IEEE international symposium on circuits and systems (ISCAS) (pp. 3024–3027).

  17. Yousif, A., Rashdan, M., Haslett, J., & Maundy, B. (2008). A low power and high speed ppm design for ultra wideband communications. In The Canadian conference on electrical and computer engineering (CCECE), Niagra falls, Canada (pp. 1055–1058).

Download references

Acknowledgements

This work was supported by the provincial iCORE program, by NSERC, and by the University of Calgary.

Author information

Authors and Affiliations

  1. Electrical Engineering Department, The American University of the Middle East, Egaila, Kuwait

    Mostafa Rashdan

Authors
  1. Mostafa Rashdan
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Mostafa Rashdan.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Rashdan, M. Effect of PVT variations on differential-time signaling data link architecture. Analog Integr Circ Sig Process 99, 71–79 (2019). https://doi.org/10.1007/s10470-018-1304-4

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10470-018-1304-4

Keywords

Search

Navigation