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Design and analysis of a feedback time difference amplifier with linear and programmable gain

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Abstract

This paper proposes a feedback time difference amplifier (FTDA) that achieves linear, controllable gain and changeable input range for different time difference gains. The proposed FTDA consists of two identical feedback output generators. The feedback output generator achieves a linear input–output transfer characteristic by employing two p-type keepers for time gain feedback control. Its validity was demonstrated using \({0.13}\, {\upmu \hbox {m}}\) SiGe BiCMOS process. The power consumption is \(91.54 \,{\upmu \hbox {W}}\) for the highest gain with input signals at \({2}\,\hbox {MHz}\). The gain can be controlled from 25.06 to \(734.9\,{\hbox {s/s}}\) within \(40 \,\hbox {ps}\) input time interval.

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References

  1. Henzler, S. (2010). Time-to-digital converters. New York: Springer.

    Book  Google Scholar 

  2. Hsu, C. M., Straayer, M., & Perrott, M. (2008). A low-noise, wide-BW 3.66 Hz digital fractional-n frequency synthesizer with a noise-shaping time-to-digital converter and quantization noise cancellation. In ISSCC 2008 digest of technical papers (pp. 340–341).

  3. Niitsu, K., Sakurai, M., Harigai, N., Yamaguchi, J., & Kobayashi, H. (2012). CMOS circuits to measure timing jitter using a self-referenced clock and a cascaded time difference amplifier with duty-cycle compensation. IEEE Journal of Solid-State Circuits, 47(11), 2701–2710.

    Article  Google Scholar 

  4. Villa, F., Lussana, R., Bronzi, D., Tisa, S., Tosi, A., Zappa, F., et al. (2014). Cmos imager with 1024 spads and tdcs for single-photon timing and 3-D time-of-flight. IEEE Journal of selected topics in quantum electronics, 20(6), 364–373.

    Article  Google Scholar 

  5. Abas, A. M., Bystrov, A., Kinniment, D. J., Maevsky, O. V., Russell, G., & Yakovlev, A. V. (2002). Time difference amplifier. Electronics Letters, 38(23), 1437–1438.

    Article  Google Scholar 

  6. Lee, M., & Abidi, A. A. (2008). A 9 b, 1.25 ps resolution coarse-fine time-to-digital converter in 90 nm CMOS that amplifies a time residue. IEEE Journal of Solid-State Circuits, 43(4), 769–777.

    Article  Google Scholar 

  7. Mandai, S., Iizuka, T., Nakura, T., Ikeda, M., & Asada, K. (2010). Time-to-digital converter based on time difference amplifier with non-linearity calibration. In Proceedings of the ESSCIRC, 2010 (pp. 266–269). IEEE.

  8. Nakura, T., Mandai S., Ikeda, M., & Asada, K. (2009). Time difference amplifier using closed-loop gain control. In 2009 symposium on VLSI circuits (pp. 208–209). IEEE.

  9. Dehlaghi, B., Magierowski, S., & Belostotski, L. (2011). Highly-linear time-difference amplifier with low sensitivity to process variations. Electronics Letters, 47(13), 743–745.

    Article  Google Scholar 

  10. Kwon, H.-J., Lee, J.-S., Sim, J.-Y., & Park, H.-J. (2011). A high-gain wide-input-range time amplifier with an open-loop architecture and a gain equal to current bias ratio. In IEEE Asian solid state circuits conference (A-SSCC), 2011 (pp. 325–328). IEEE.

  11. Kim, K. S., Kim, Y.-H., Yu, W., & Cho, S. H. (2013). A 7 bit, 3.75 ps resolution two-step time-to-digital converter in 65 nm cmos using pulse-train time amplifier. IEEE Journal of Solid-State Circuits, 48(4), 1009–1017.

    Article  Google Scholar 

  12. Baker, R. J. (2008). CMOS: Circuit design, layout, and simulation (Vol. 1). Hoboken: Wiley.

    Book  Google Scholar 

  13. Alahmadi, A. N. M., Russell, G., & Yakovlev, A. (2012). Reconfigurable time interval measurement circuit incorporating a programmable gain time difference amplifier. In IEEE 15th international symposium on design and diagnostics of electronic circuits & systems (DDECS), 2012 (pp. 366–371). IEEE.

  14. Heo, M., Kwon, D., & Lee, M. (2014). Low-power programmable high-gain time difference amplifier with regeneration time control. Electronics Letters, 50(16), 1129–1131.

    Article  Google Scholar 

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Correspondence to Wenlan Wu.

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Wu, W., Baker, R.J., Bikkina, P. et al. Design and analysis of a feedback time difference amplifier with linear and programmable gain. Analog Integr Circ Sig Process 94, 357–367 (2018). https://doi.org/10.1007/s10470-017-1062-8

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  • DOI: https://doi.org/10.1007/s10470-017-1062-8

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