Abstract
This work presents a current reference circuit fabricated in a standard 0.18 μm CMOS technology. The reference current is obtained by applying thermal compensation voltage in the conventional self-biased or beta multiplier-based current reference circuit. Eight prototypes of the proposed architecture were measured which have resulted into the mean reference current of 26.1 nA with the temperature coefficient of 202.1 ppm/°C. These measurements were performed in the temperature range of − 40 to + 85 °C. The circuit is capable of working over the supply voltage range of 1–2 V with the measured mean line sensitivity of 2.18%/V. The maximum measured power dissipation of the circuit is 104 nW at 2 V.
References
Alioto, M. (2012). Ultra-low power VLSI circuit design demystified and explained: A tutorial. IEEE Transactions on Circuits and Systems I: Regular Papers, 59(1), 3–29.
De Vita, G., & Iannaccone, G. (2007). A 109 nW, 44 ppm/°C CMOS current reference with low sensitivity to process variations. In Proceedings of IEEE international symposium on circuits and systems, New Orleans, LA (pp. 3804–3807).
Yoo, C., & Park, J. (2007). CMOS current reference with supply and temperature compensation. Electronics Letters, 43(25), 1422–1424.
Song, L., & Baker, R. J. (1989). Process and temperature performance of a CMOS beta-multiplier voltage reference. In Proceedings of Midwest symposium on circuits and systems, Notre Dame, IN (pp. 33–36).
Osipov, D., & Paul, S. (2017). Temperature-compensated β-multiplier current reference circuit. IEEE Transactions on Circuits and Systems II: Express Briefs, 64(10), 1162–1166.
Chouhan, S. S., & Halonen, K. (2016). A 0.67 μW, 177 ppm/°C all MOS current reference circuit in 0.18 μm CMOS technology. IEEE Transactions on Circuits and Systems II Express. Briefs, 63(8), 723–727.
Filanovsky, I. M., & Allam, A. (2001). Mutual compensation of mobility and threshold voltage temperature effects with applications in CMOS circuits. IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications, 48(7), 876–884.
Magnelli, L., Crupi, F., Corsonello, P., Pace, C., & Iannaccone, G. (2011). A 2.6 nW, 0.45 V temperature-compensated subthreshold CMOS voltage reference. IEEE Journal of Solid-State Circuits, 46(2), 465–474.
Camacho-Galeano, E. M., Galup-Montoro, C., & Schneider, M. C. (2005). A 2-nW 1.1-V self-biased current reference in CMOS technology. IEEE Transactions on Circuits and Systems II Express Briefs, 52(2), 61–65.
Hirose, T., Osaki, Y., Kuroki N., & Numa, M. (2010). A nano-ampere current reference circuit and its temperature dependence control by using temperature characteristics of carrier mobilities. In Proceedings of the ESSCIRC, Seville (pp. 114–117).
Acknowledgements
This work is funded by the TEKES Project Dnro 3246/31/2014 of the Tekes-the Finnish Funding Agency for Innovation Finland and the CIMO (Centre of International Mobility) Grant No: Intia-1-2016-03.
Author information
Authors and Affiliations
Corresponding author
Rights and permissions
About this article
Cite this article
Chouhan, S.S., Halonen, K. Ultra low power beta multiplier-based current reference circuit. Analog Integr Circ Sig Process 93, 523–529 (2017). https://doi.org/10.1007/s10470-017-1057-5
Received:
Revised:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s10470-017-1057-5