Skip to main content
SpringerLink
Log in

Low power PLL with reduced reference spur realized with glitch-free linear PFD and current splitting CP

  • Published:
Analog Integrated Circuits and Signal Processing Aims and scope Submit manuscript

Abstract

This work has been focused on designing a phase locked loop (PLL) operating in the GHz range with reduced reference spur and power requirement suitable for wireless communication applications such as wireless receivers, serial link trans-receivers and military communication. A novel PLL is designed using a linear PFD which is free of glitches, dead zone and blind zone, a charge pump based on current splitting technique and a modified current starved differential delay cell (MCSDD) VCO. Performance characteristics of proposed PLL obtained from circuit simulation in Cadence have been compared with simulation results from MATLAB. φ–V characteristics of linear PFD has been found to offer better linearity from −π to π as blind zone and dead zone are eliminated. Glitches at output of PFD have also been eliminated. Charge pump based on current splitting technique in combination with proposed PFD has been found to be effective in reducing leakage current to 3 nA. Tuning range of 98.12% with maximum operating frequency of 4.27 GHz has been obtained for the MCSDD VCO. PLL built with above circuits has been found to offer reference spur of −75.92 dBc@20 MHz offset, phase noise of −113.5 dBc/Hz@100 kHz and lock time of 2.95 μs. It is believed to be the first report of linear PFD in which glitches are completely eliminated. The PLL would be suitable for low power, low noise and high frequency applications as required in mobile communications operating around 20 MHz, to be derived from the VCO when set to generate a frequency of 2.56 GHz.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13
Fig. 14
Fig. 15
Fig. 16
Fig. 17

Similar content being viewed by others

References

  1. Abdul Majeed, K.K., & Kailath, B.J. (2013). Low power, high frequency, free dead zone PFD for a PLL design. In IEEE faible tension faible consommation, 20–21 June (vol. 1, no. 4, pp. 20–21).

  2. Abdul Majeed, K. K., & Kailath, B. J. (2013). A novel phase frequency detector for a high frequency PLL design. Procedia Engineering, 64, 377–384.

    Article  Google Scholar 

  3. Abdul Majeed, K.K., & Kailath, B.J. (2015). CMOS current starved voltage controlled oscillator circuit for a fast locking PLL. In Annual IEEE India conference (INDICON), 17–20 December, New Delhi (pp. 1–5).

  4. Chen, W.-H., Inerowicz, M. E., & Jung, B. (2010). Phase frequency detector with minimal blind zone for fast frequency acquisition. IEEE Transactions on Circuits and Systems II: Express Briefs, 57(12), 936–940.

    Article  Google Scholar 

  5. Gardner, F. M. (1980). Charge-pump phase-lock loops. IEEE Transactions on Communications, 28(11), 1849–1858.

    Article  Google Scholar 

  6. Hanumolu, P. K., Brownlee, M., Mayaram, K., & Moon, U.-K. (2004). Analysis of charge-pump PLL. IEEE Transactions on Circuits and Systems I: Regular Papers, 51(9), 1665–1674.

    Article  Google Scholar 

  7. Homayoun, A., & Razavi, M. (2013). Analysis of phase noise in phase/frequency detectors. IEEE Transactions on Circuits and Systems I: Regular Papers, 60(3), 529–539.

    Article  MathSciNet  Google Scholar 

  8. Hsu, C.W., Tripurari, K., Yu, S.A., & Kinget, P.R. (2011). A 2.2 GHz PLL using a phase-frequency detector with an auxiliary sub-sampling phase detector for in-band noise suppression. In IEEE custom integrated circuits conference, 19–21 September, San Jose, CA (pp. 1–4).

  9. Hsu, C.-W., Tripurari, K., Yu, S.-A., & Kinget, P. R. (2015). A sub-sampling-assisted phase-frequency detector for low-noise PLLs with robust operation under supply interference. IEEE Transactions on Circuits and Systems I: Regular Papers, 62(1), 90–99.

    Article  Google Scholar 

  10. Huang, P.-C., Chang, W.-S., & Lee, T.-C. (2014). 21.2 A 2.3 GHz fractional-N divider less phase-locked loop with −112dBc/Hz in-band phase noise. In IEEE international solid-state circuits conference digest of technical papers, 9–13 February (vol. 9, no. 13, pp. 362–363).

  11. Ismail, N.M.H., & Othman, M. (2009). CMOS phase frequency detector for high speed applications. In International conference on microelectronics, 19–22 December (pp. 201–204).

  12. Jalalifar, M., & Byun, G.-S. (2013). Near-threshold charge pump circuit using dual feedback loop. Electronics Letters, 49(23), 1436–1438.

    Article  Google Scholar 

  13. Kamal, N., Al-Sarawi, S. F., & Abbott, D. (2013). Reference spur suppression technique using ratioed current charge pump. Electronics Letters, 49(12), 746–747.

    Article  Google Scholar 

  14. Larsson, P. (1995). Reduced pull-in time of PLL using a simple nonlinear phase detector. IEE Proceedings Communications, 142(4), 221–222.

    Article  Google Scholar 

  15. Lee, J.-S., Keel, M.-S., Lim, S.-I., & Kim, S. (2000). Charge pump with perfect current matching characteristics in phase-locked loops. Electronics Letters, 36(23), 1907–1908.

    Article  Google Scholar 

  16. Lim, K., Park, C.-H., Kim, D.-S., & Kim, B. (2000). A low-noise PLL design by loop BW optimization. IEEE Journal of Solid-State Circuits, 35(6), 807–815.

    Article  Google Scholar 

  17. Lin, M., Erdogan, A.T., Arslan, T., & Stoica, A. (2007). A fast pull-in scheme of plls using a triple path nonlinear phase frequency detector. In IEEE international SOC conference, 26–29 September (pp. 105–108).

  18. Mansuri, M., Liu, D., & Yang, C.-K. K. (2002). Fast frequency acquisition phase-frequency detectors for Gsamples/s phase-locked loops. IEEE Journal of Solid-State Circuits, 37(10), 1331–1334.

    Article  Google Scholar 

  19. Tang, Y., Ismail, M., & Bibyk, S. (2002). A new fast-settling gearshift adaptive PLL to extend loop bandwidth enhancement in frequency synthesizers. IEEE International Symposium on Circuits and Systems, 4, IV-787–IV-790.

    Google Scholar 

  20. Woo, K., Liu, Y., Nam, E., & Ham, D. (2008). Fast-lock hybrid PLL combining fractional-N and Integer-N modes of differing bandwidths. IEEE Journal of Solid-State Circuits, 43(2), 379–389.

    Article  Google Scholar 

  21. Xiangning, F., Bin, L., Likai, Y., & Yujie, W. (2012). CMOS phase frequency detector and charge pump for wireless sensor networks. In IEEE MTT-S international microwave workshop series on millimeter wave wireless technology and applications, 18–20 September (pp. 1–4).

  22. Yang, C.-Y., & Liu, S.-I. (2000). Fast-switching frequency synthesizer with a discriminator-aided phase detector. IEEE Journal Solid-State Circuits, 35(10), 1445–1452.

    Article  Google Scholar 

  23. Zhang, C., & Syrzycki, M. (2010). Modifications of a dynamic-logic phase frequency detector for extended detection range. In IEEE international midwest symposium on circuits and systems, 1–4 August (pp. 105–108).

Download references

Author information

Authors and Affiliations

  1. Department of Electronics, MEA Engineering College, Shihab Thangal Nagar, Vengoor Post, Malappuram, Kerala, India

    K. K. Abdul Majeed

  2. Indian Institute of Information Technology Design and Manufacturing (IIITDM) Kancheepuram, Chennai, India

    Binsu J. Kailath

Authors
  1. K. K. Abdul Majeed
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Binsu J. Kailath
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to K. K. Abdul Majeed.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Abdul Majeed, K.K., Kailath, B.J. Low power PLL with reduced reference spur realized with glitch-free linear PFD and current splitting CP. Analog Integr Circ Sig Process 93, 29–39 (2017). https://doi.org/10.1007/s10470-017-1013-4

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10470-017-1013-4

Keywords

Search

Navigation