Skip to main content
Log in

A novel 9T SRAM architecture for low leakage and high performance

  • Published:
Analog Integrated Circuits and Signal Processing Aims and scope Submit manuscript

Abstract

A novel 9T-SRAM architecture is proposed in this paper. It smartly integrates the source biasing and body-bias control schemes in designing an SRAM cell. The proposed cell consists of nine transistors with separate read/write ports. It uses a read word-line based body bias controller and two tail transistors in pull-down path to improve the design metrics. The main objective of the proposed architecture is to minimize the leakage current in an SRAM cell while improving the stability and reducing the read/write delays. The above design metrics of the circuit are compared with the conventional 6T, LP10T and WRE8T SRAM cells under process and temperature variations. It is observed that as compared to conventional SRAM, the proposed 9T SRAM architecture (8 × 16 arrays) reduces static power consumption by 98%, improves the read and write stability by 66.07 and 10.51% respectively. Again, the write delay is reduced to about 95% while read delay is minimized to about 64.1% under different body-bias voltages.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12

Similar content being viewed by others

Abbreviations

SRAM:

Static random access memory

SoC:

System on chip

MOSFET:

Metal oxide semiconductor field effect transistor

FinFET:

Fin shaped field effect transistor

SOI:

Silicon on insulator

RWL:

Read word line

WWL:

Write word line

BL:

Bit line

RBL:

Read bit line

WBL:

Write bit line

CMOS:

Complementary metal oxide semiconductor

BBC:

Body bias controller

PTM:

Predictive technology model

FBB:

Forward body biased

RBB:

Reverse body biased

RSNM:

Read static noise margin

WSNM:

Write static noise margin

HSNM:

Hold static noise margin

PD:

Proposed design

Vt :

Threshold voltage

References

  1. Wang, K. (2010). Ultra low-power fault-tolerant SRAM design in 90 nm CMOS technology’, M.S. thesis, Department of Electrical and Computer Engineering, University of Saskatchewan, Saskatoon, SK, Canada.

  2. International Technology Roadmap for Semiconductors. 2012. http://www.itrs.net/Links/2012ITRS/Home2012.htm.

  3. Chandrakasan, A. P., Daly, D. C., Finchelstein, D. F., Kwong, J., Ramadass, Y. K., Sinangil, M. E., et al. (2010). Technologies for ultra-dynamic voltage scaling. Proceedings of the IEEE, 98(2), 191–214.

    Article  Google Scholar 

  4. Rabaey, J. M., Chandrakasan, A. P., & Nikolic, B. (2003). Digital integrated circuits: A design perspective. Upper saddle river, NJ, USA: Prentice-Hall.

    Google Scholar 

  5. Yang, Y., Park, J., Song, S. C., Wang, J., Yeap, G., & Jung, S. O. (2015). Single-ended 9T SRAM cell for near-threshold voltage operation with enhanced read performance in 22-nm FinFET technology. IEEE Transaction on Very Large Scale Integration, 23(11), 2748–2752.

    Article  Google Scholar 

  6. Dreslinski, R. G., Wieckowski, M., Blaauw, D., Sylvester, D., & Mudge, T. (2010). Near-threshold computing: reclaiming moore’s law through energy efficient integrated circuits. Proceedings of the IEEE, 98(2), 253–266.

    Article  Google Scholar 

  7. Bansal, A., Mukhopadhyay, S., & Roy, K. (2007). Device-optimization technique for robust and low-power FinFET SRAM design in nanoscaleera. IEEE Transactions on Electron Devices, 54(6), 1409–1419.

    Article  Google Scholar 

  8. Singh, J., Pradhan, D. K., Hollis, S., & Mohanty, S. P. (2008). A single ended 6T SRAM cell design for ultra-low-voltage applications. IEICE Electronics Express, 5(6), 750–755.

    Article  Google Scholar 

  9. Mizuno, H., & Nagano, T. (1996). Driving source-line cell architecture for sub-1-V high-speed low-power applications. IEEE Journal of Solid-State Circuits, 31(4), 552–557.

    Article  Google Scholar 

  10. Kolar, P., Karl, E., Bhattacharya, U., et al. (2011). A 32 nm High-k metal gate SRAM with adaptive dynamic stability enhancement for low-voltage operation. IEEE Journal of Solid-State Circuits, 46(1), 76–84.

    Article  Google Scholar 

  11. Ahmadimehr, A.-R., Ebrahimi, B., Afzali-Kusha, A. (2009). A high speed sub threshold SRAM cell design. In: Proceedings of Quality Electronic Design, ASQED 2009. 1st Asia Symposium on, 2009, pp. 9–13.

  12. Zhai, B., Blaauw, D., Sylvester, D., Hanson, S. (2007) A sub-200 mV 6T SRAMin 0.13 µmCMOS’. In: IEEE International Solid-State Circuits Conference Dig. Tech. Papers, 2007, pp. 332–606.

  13. Calhoun, B. H., Chandrakasan, A. (2006) A 256 kb sub-threshold SRAM in 65 nm CMOS. In: IEEE International Solid-State Circuits Conf. Dig. Tech. papers, 2006, pp. 628–629.

  14. Kim, T. H., Liu, J., Keane, J., Kim, C. H. (2007). A high-density sub threshold SRAM with data-independent bit line leakage and virtual ground replica scheme. In: IEEE International Solid-State Circuits Conference Dig. Tech. Papers, 2007, pp. 330–606.

  15. Kulkarni, J. P., Kim, K., & Roy, K. (2007). A 160 mV robust Schmitt Trigger based sub threshold SRAM. IEEE Journal of Solid-State Circuits, 42(10), 2303–2313.

    Article  Google Scholar 

  16. Kim, C. H., Roy, K. (2002). DynamicVt SRAM: A leakage tolerant cache memory for low voltage microprocessors. In: Proceedings of International Symposium Low Power Electron. Des, August 2002, pp. 251–254.

  17. Moradi, F., Wisland, D. T., Mahmoodi, H., Berg, Y., Cao, T.V. (2010). New SRAM design using body bias technique for ultra low power applications. In: 11th International Symposium on Quality Electronic Design, 2010.

  18. Zhai, B., Hanson, S., Blaauw, D., & Sylvester, D. (2008). A variation-tolerant sub-200 mV 6-T sub-threshold SRAM. IEEE Journal of Solid-State Circuits, 43(10), 2338–2348.

    Article  Google Scholar 

  19. Moradi, F., Wisland, D. T. (2009). Adaptive supply voltage circuit using body bias technique. MIXDES 2009, In: 16th International Conference on Mixed Design of Integrated Circuits and Systems, June 25–27.

  20. Islam, A., & Hasan, M. (2012). Leakage characterization of 10T SRAM cell. IEEE Transactions on Electron Devices, 59(3), 631–638.

    Article  Google Scholar 

  21. Pasendiand, G., & Fakhraie, S. M. (2014). An 8T low voltage and low leakage half selection disturb free SRAM using Bulk-CMOS and FinFETs. IEEE Transactions on Electron Devices, 61(7), 2357–2363.

    Article  Google Scholar 

  22. http://ptm.asu.edu/

  23. Zhang, L., Wu, C., Feng Mao, L., & Zheng, J. (2012). Integrated SRAM compiler with clamping diode to reduce leakage and dynamic power in nano-CMOS process. IET Micro & Nano Letters, 7(2), 171–173.

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Rohit Lorenzo.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Lorenzo, R., Chaudhury, S. A novel 9T SRAM architecture for low leakage and high performance. Analog Integr Circ Sig Process 92, 315–325 (2017). https://doi.org/10.1007/s10470-017-0997-0

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10470-017-0997-0

Keywords

Navigation