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High-speed single-channel SAR ADC with a novel control logic in 65 nm CMOS

  • Mixed Signal Letter
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Abstract

This paper presents an 8-bit 320 MS/s single-channel successive approximation register (SAR) analog-to-digital converter (ADC) with low power consumption. Through a procedure of splitting all the most significant bit (MSB) capacitors except the least significant bit (LSB) capacitor into two equal sub-capacitors and reusing the terminal capacitor, the average switching energy and total capacitance can be reduced by about 87 and 50% respectively compared to the conventional procedure. Meanwhile, high-speed operation can be achieved by using a novel SAR control logic featuring efficient hardware cost and small critical path delay. In addition, this paper analyzes how to obtain the value of the unit capacitance which exhibits trade-offs between conversion rate, power consumption and linearity performance. The SAR ADC is simulated in 65 nm CMOS technology. It can achieve 48.63 dB SNDR, 63.61 dB SFDR at a supply voltage of 1.2 V and sampling frequency of 320 MS/s for near-Nyquist input, consuming 2.59 mW of power and with a FoM of 37 fJ/conversion-step.

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Acknowledgments

This work was supported by the National Natural Science Foundation of China (61625403, 61674118)

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Authors and Affiliations

  1. School of Microelectronics, Xidian University, Xi’an, 710071, People’s Republic of China

    Tao Wang, Zhangming Zhu, Liang Zhang & Yintang Yang

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  1. Tao Wang
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  2. Zhangming Zhu
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  3. Liang Zhang
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  4. Yintang Yang
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Correspondence to Zhangming Zhu.

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Wang, T., Zhu, Z., Zhang, L. et al. High-speed single-channel SAR ADC with a novel control logic in 65 nm CMOS. Analog Integr Circ Sig Process 91, 503–511 (2017). https://doi.org/10.1007/s10470-017-0964-9

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  • DOI: https://doi.org/10.1007/s10470-017-0964-9

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