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Design of new practical phase shaping circuit using optimal pole–zero interlacing algorithm for fractional order PID controller

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An Erratum to this article was published on 20 February 2017

Abstract

This paper presents the implementation of fractional order PID (FO-PID) controller using hardwired modules of constant phase element (CPE). A new approach of phase shaping by slope cancellation of asymptotic phase plots for zeros and poles within the given bandwidth is realized. Analog circuits, which exhibit analog fractional-order integrator and fractional-order differentiator, are used for building the FO-PID controller. The design procedure is developed to obtain the optimal pole–zero pairs and respective “Fractance” components to realize for any value of fractional differ-integrator. These CPE elements give minimum error tolerance over the set phase value by using commercially available (R–C) components and Op-Amps. The pole–zero location in the root locus plot with constant asymptotic angle under various feed-forward gains is achieved with these analog integrodifferential circuits of the FO-PID. The iso-damping feature of the controller is practically demonstrated. A comparative performance is demonstrated under various settings of feed forward gains, which indicate the constant overshoot with FO-PID against the conventional PID. These circuits are developed and implemented with a DC motor emulator to confirm the designed performance of the controller.

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Acknowledgements

The authors would like to thank the support provided by the Board of Research of Nuclear sciences of the Department of Atomic Energy, India, under the Project Sanction No. 2007/36/81-BRNS/2907 and 2012/36/69-BRNS/2951.

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Authors and Affiliations

  1. Visvesvaraya National Institute of Technology, Nagpur, MH, India

    Mohan V. Aware, Anjali S. Junghare, Swapnil W. Khubalkar, Ashwin Dhabale & Rutuja Dive

  2. Bhabha Atomic Research Center (BARC), Mumbai, MH, India

    Shantanu Das

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  1. Mohan V. Aware
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  2. Anjali S. Junghare
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  3. Swapnil W. Khubalkar
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Correspondence to Swapnil W. Khubalkar.

Additional information

The original version of this article was revised: Fig. 4 has been incorrectly published in the online version. This has been corrected in this version.

An erratum to this article is available at http://dx.doi.org/10.1007/s10470-017-0946-y.

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Aware, M.V., Junghare, A.S., Khubalkar, S.W. et al. Design of new practical phase shaping circuit using optimal pole–zero interlacing algorithm for fractional order PID controller. Analog Integr Circ Sig Process 91, 131–145 (2017). https://doi.org/10.1007/s10470-016-0920-0

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